New header file cpu-mmu.h is added and move mmu relative function
declaration to this file.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu-mmu.h| 30 ++
target/loongarch/cpu.c| 1 +
target/loongarch/cpu_helper.c | 1 +
target/loongarch
Function loongarch_check_pte() can get physical address and access
priviledge, it works on both TLB entry and pte entry. It can be used
at page table walking.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 35 ++-
1 file changed, 10 insertions(+), 25
On LoongArch system, there are two pages with one TLB entry. If the
whole TLB entry is flushed, two pages will be flushed. Otherwise if
tlb is flushed one by one, page size is one page at a time.
Also virtual address of odd page is fixed here.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg
Qemu TCG provides some tlb flushing API, tlb can be flushed with
specified mmu idx and virtual address. Here fine-grained tlb flush
method is used.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/tlb_helper.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff
With API tlb_flush_range_by_mmuidx(), bitmap method of mmu idx should
be used rather than itself. Also mmu idx comes from page table entry
information rather current running mode. With page table entry,
global bit for MMU_KERNEL_IDX, otherwise it is MMU_USER_IDX.
Signed-off-by: Bibo Mao
-by: Bibo Mao
---
target/loongarch/cpu.c | 180 -
target/loongarch/cpu.h | 2 -
2 files changed, 90 insertions(+), 92 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index abad84c054..b96429ffb1 100644
--- a/target/loongarch
bitmap method with mmu idx, page size and address
calculation
---
Bibo Mao (9):
target/loongarch: Move some function definition to kvm directory
target/loongarch: Define function loongarch_cpu_post_init as static
target/loongarch: Set page size in TLB misc with STLB
target/loongarch: Add
Move function definition specified with kvm to the corresponding
directory. Also remove header file "cpu.h" including outside of
macro QEMU_KVM_LOONGARCH_H.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 1 +
target/loongarch/cpu.h | 9 ---
entries, even with
STLB, it is convenient with TLB maintainance operation.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/tlb_helper.c | 41 ---
1 file changed, 10 insertions(+), 31 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c
b/target/loongarch/tcg
Common function loongarch_check_pte() is to check tlb entry, return
the physical address and access priviledge. Also it can be used with
page table entry, which is used in page table walker.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu-mmu.h| 8
target/loongarch/cpu_helper.c
l be better if tcg_enabled() is used here, since
CONFIG_TCG and CONFIG_KVM is enabled by default. It should be supported
in KVM mode now. It is suggested in V4 review process :)
Regards
Bibo Mao
+object_class_property_add(oc, "avecintc", "OnOffAuto",
+
inal sentence work?
env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
This piece of code is a little strange.
Regards
Bibo Mao
+} else {
+env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
+}
if (FIELD_EX64
range to declare new variable between sentences, I think it
should be put in the beginning of function.
Regards
Bibo Mao
+for (int cpu = 0; cpu < ms->smp.cpus; cpu++) {
+cpu_state = qemu_get_cpu(cpu);
+cpudev = DEVICE(cpu_state);
+
GARCH_AVEC(opaque);
+uint64_t msg_addr = addr + VIRT_AVEC_BASE;
+cpu_num = FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM);
Here is physical cpuid rather than logic cpu index. We need convert
physical cpuid to logic cpu index.
Regards
Bibo Mao
+irq_num = FIELD_EX64(msg_addr, MSG_ADDR, IRQ_NUM
VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, 4),
ditto, it will be better if there is macro replaced with 4.
Regards
Bibo Mao
+VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU),
+VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU),
+VMSTATE_END_OF_LIST()
+},
+};
+
static co
val;
addr = malloc(100);
*(int *)addr = 1;
addr1 = 0xULL + addr;
val = *(int *)addr1;
printf("val %d \n", val);
}
Cc: qemu-sta...@nongnu.org
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 4 ++--
1 file changed, 2
The following changes since commit df6fe2abf2e990f767ce755d426bc439c7bba336:
Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into
staging (2025-07-07 09:22:41 -0400)
are available in the Git repository at:
https://github.com/bibo-mao/qemu.git tags/pull
unnecessary in tlb entry fill path.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
target/loongarch/tcg/tlb_helper.c | 27 ++-
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c
b/target/loongarch/tcg/tlb_helper.c
index
Memory about LoongArchExtIOICommonState::cpu is allocated in common
code, it had better be freed in common code also.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi.c| 9 -
hw/intc/loongarch_extioi_common.c | 9 +
include/hw
Function helper_csrwr_stlbps() is emulation with CSR STLBPS register
write operation. However there is only parameter checking action, and
no register updating action. Here update value of CSR_STLBPS when
parameter passes to check.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
target
There is small typo issue in function helper_csrwr_pwcl(), this patch
corrects this issue.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
target/loongarch/tcg/csr_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/tcg/csr_helper.c
b/target
On 2025/7/10 下午8:43, Stefan Hajnoczi wrote:
On Thu, Jul 10, 2025 at 5:34 AM Bibo Mao wrote:
The following changes since commit df6fe2abf2e990f767ce755d426bc439c7bba336:
Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into
staging (2025-07-07 09:22:41 -
Function helper_csrwr_stlbps() is emulation with CSR STLBPS register
write operation. However there is only parameter checking action, and
no register updating action. Here update value of CSR_STLBPS when
parameter passes to check.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
target
The following changes since commit df6fe2abf2e990f767ce755d426bc439c7bba336:
Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into
staging (2025-07-07 09:22:41 -0400)
are available in the Git repository at:
https://github.com/bibo-mao/qemu.git tags/pull
unnecessary in tlb entry fill path.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
target/loongarch/tcg/tlb_helper.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c
b/target/loongarch/tcg/tlb_helper.c
index dc48b0f4d2
Memory about LoongArchExtIOICommonState::cpu is allocated in common
code, it had better be freed in common code also.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi.c| 9 -
hw/intc/loongarch_extioi_common.c | 9 +
include/hw
There is small typo issue in function helper_csrwr_pwcl(), this patch
corrects this issue.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
target/loongarch/tcg/csr_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/tcg/csr_helper.c
b/target
irq = -1;
How about irq = BIT(31), the other bits keeps zero except bit 31?
Regards
Bibo Mao
+}
+
+return irq;
+}
+
target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val)
{
int64_t old_v = env->CSR_ESTAT;
diff --git a/target/loongarch/tcg/helper.h b/targe
+}
+
if (kvm_enabled()) {
kvm_loongarch_set_interrupt(cpu, irq, level);
} else if (tcg_enabled()) {
modification estat should be put here.
Regards
Bibo Mao
num / 64]);
+qemu_set_irq(s->cpu[cpu_num].parent_irq, 1);
+}
+qemu_set_irq(s->cpu[cpu_num].parent_irq, level);
There is double function call with qemu_set_irq().
Regards
Bibo Mao
+}
+
static void loongarch_avec_mem_write(void *opaque, hwaddr addr,
be renamed as virt_has_avecintc()?
Regards
Bibo Mao
+ret |= BIT(IOCSRF_AVEC);
+}
if (kvm_enabled()) {
ret |= BIT(IOCSRF_VM);
}
@@ -624,6 +631,10 @@ static MemTxResult virt_iocsr_misc_read(void *opaque,
hwaddr addr,
if (
re & BIT(IOCSRF_AVEC))) {
+return false;
+}
There had better be one empty line, however it is up to you since I am
not good at coding style.
Regards
Bibo Mao
+return true;
+}
+
static inline bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms)
{
if (lvms->veiointc == ON_OFF_AUTO_OFF) {
e, %s/dfine/define/
"move some machine dfine to virt.h"
otherwise look good to me.
Reviewed-by: Bibo Mao
-by: Bibo Mao
---
target/loongarch/cpu.c | 180 -
target/loongarch/cpu.h | 2 -
2 files changed, 90 insertions(+), 92 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index abad84c054..b96429ffb1 100644
--- a/target/loongarch
entries, even with
STLB, it is convenient with TLB maintainance operation.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/tlb_helper.c | 41 ---
1 file changed, 10 insertions(+), 31 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c
b/target/loongarch/tcg
New header file cpu-mmu.h is added and move mmu relative function
declaration to this file.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu-mmu.h| 30 ++
target/loongarch/cpu.c| 1 +
target/loongarch/cpu_helper.c | 1 +
target/loongarch
Function loongarch_check_pte() can get physical address and access
priviledge, it works on both TLB entry and pte entry. It can be used
at page table walking.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 35 ++-
1 file changed, 10 insertions(+), 25
table walk emluation in future.
Bibo Mao (6):
target/loongarch: Move some function definition to kvm directory
target/loongarch: Define function loongarch_cpu_post_init as static
target/loongarch: Set page size in TLB misc with STLB
target/loongarch: Add header file cpu-mmu.h
target
Common function loongarch_check_pte() is to check tlb entry, return
the physical address and access priviledge. Also it can be used with
page table entry, which is used in page table walker.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu-mmu.h| 9 +
target/loongarch/cpu_helper.c
Move function definition specified with kvm to the corresponding
directory. Also remove header file "cpu.h" including outside of
macro QEMU_KVM_LOONGARCH_H.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 1 +
target/loongarch/cpu.h | 9 ---
New header file cpu-mmu.h is added and move mmu relative function
declaration to this file.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu-mmu.h| 30 ++
target/loongarch/cpu.c| 1 +
target/loongarch/cpu_helper.c | 1 +
target/loongarch
table walk emluation in future.
Bibo Mao (6):
target/loongarch: Move some function definition to kvm directory
target/loongarch: Define function loongarch_cpu_post_init as static
target/loongarch: Set page size in TLB misc with STLB
target/loongarch: Add header file cpu-mmu.h
target
On 2025/7/7 下午2:36, lixianglai wrote:
Hi Bibo Mao:
On 2025/6/13 上午9:31, Xianglai Li wrote:
The expire time is sent to the timer only
when the expire Time is greater than 0 or
greater than now. Otherwise, the timer
will trigger interruption continuously.
Timer interrupts are sent using
On 2025/7/2 下午3:21, gaosong wrote:
在 2025/7/2 上午11:15, Bibo Mao 写道:
On 2025/6/27 上午11:01, Song Gao wrote:
Implement avec set irq and update CSR_MSIS and CSR_MSGIR.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 44 ++--
1 file changed, 42
On 2025/7/2 下午3:10, gaosong wrote:
在 2025/7/2 上午10:03, Bibo Mao 写道:
On 2025/6/27 上午11:01, Song Gao wrote:
LoongArchVirtMachinState adds avecintc features, and
it use to check whether virt machine support advance interrupt
controller
and default set avecintc = ON_OFF_AUTO_ON
{
+if (!(lvms->misc_feature & BIT(IOCSRF_AVEC))) {
+return false;
+ }
+
+if (lvms->avecintc == ON_OFF_AUTO_OFF) {
+return false;
+}
Is it enough to only check variable misc_feature? checking avecintc
seems unnecessary duplicated.
Regards
Bibo Mao
+return true;
+}
+
static inline bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms)
{
if (lvms->veiointc == ON_OFF_AUTO_OFF) {
if (irq == INT_AVEC) {
env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 1);
env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGINT, 1);
}
Regards
Bibo Mao
+
if (kvm_enabled()) {
kvm_loongarch_set_interrupt(cpu, irq, level);
} else if (tcg_enabled()) {
MSGIS[i]) {
+return;
+}
+}
+qemu_set_irq(s->cpu[cpu_num].parent_irq, 0);
Here such code can inject interrupt to cpu side.
if (level) {
set_bit(irq_num, &env->CSR_MSGIS[irq_num / 64]);
qemu_set_irq(s->cpu[cpu_num].parent_irq, 1);
s
on how MSI vector is allocated on VM.
Regards
Bibo Mao
^ ^ ^
| | |
+-+ +-+ +-+
| Devices | | PCH-LPC |
LoongArchCPU *cpu = opaque;
+
+return FIELD_EX64(cpu->env.cpucfg[1], CPUCFG1, MSG_INT);
For AVEC capability, there is bit MSG_INT in register cpucfg1 and bit
IOCSRF_AVEC in IOCSR FEATURE_REG register. Which should be used by real
hardware?
Regards
Bibo Mao
+}
+
+static const VMStateDescr
to config so many gpio
lines with number NR_VECTORS * s->num_cpu.
Regards
Bibo Mao
+
return;
}
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 6fb08740c2..1d4e62b1cf 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -381,7 +381,7 @@ static void virt_cpu_i
51
I suggest to split it into two patches, one is purely code moving
between header files, the other is actual code modification.
Regards
Bibo Mao
#define LOONGARCH_MAX_CPUS 256
#define VIRT_FWCFG_BASE 0x1e02UL
diff --git a/target/loongarch/cpu.h b/target/loongarc
CSR_MSGIS[4] in
CSR register emulation.
And when all bits about CSR_MSGIS[4] are cleared, parent irq can be set
with 0 such as:
qemu_set_irq(s->cpu[cpu_num].parent_irq, 0);
Regards
Bibo Mao
+}
+
static void loongarch_avec_mem_write(void *opaque, hwaddr addr,
is compatible with old machine.
Regards
Bibo Mao
VMSTATE_UINT64(kvm_state_counter, LoongArchCPU),
/* PV steal time */
VMSTATE_UINT64(env.stealtime.guest_addr, LoongArchCPU),
It will be better if check_vldi_mode() is renamed as
check_valid_vldi_mode().
Reviewed-by: Bibo Mao
On 2025/6/18 下午3:49, gaosong wrote:
Ping ! :-)
在 2025/6/5 上午9:53, Song Gao 写道:
on qemu we got an aborted error
**
ERROR:../target/loongarch/tcg/insn_trans/trans_vec.c.inc:3574:vldi_get_value
This patchset is small code cleanup with LoongArch TLB emulation.
LoongArch does not support hardware page table walker, TLB handling
is complicated compared with common architectures.
Bibo Mao (3):
target/loongarch: Correct spelling in helper_csrwr_pwcl()
target/loongarch: Fix CSR STLBPS
Function helper_csrwr_stlbps() is emulation with CSR STLBPS register
write operation. However there is only parameter checking action, and
no register updating action. Here update value of CSR_STLBPS when
parameter passes to check.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/csr_helper.c
unnecessary in tlb entry fill path.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/tlb_helper.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c
b/target/loongarch/tcg/tlb_helper.c
index dc48b0f4d2..21381ba59f 100644
--- a
There is small typo issue in function helper_csrwr_pwcl(), this patch
corrects this issue.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/csr_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/tcg/csr_helper.c
b/target/loongarch/tcg/csr_helper.c
On 2025/6/17 上午9:58, gaosong wrote:
在 2025/6/11 下午2:36, Bibo Mao 写道:
On 2025/6/9 下午6:48, Song Gao wrote:
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
On 2025/6/13 下午3:54, gaosong wrote:
在 2025/6/11 下午2:46, Bibo Mao 写道:
On 2025/6/9 下午6:48, Song Gao wrote:
LoongArchVirtMachinState add avecintc features, and
it use to check whether virt machine support advance interrupt
controller
and default is on.
Signed-off-by: Song Gao
---
hw
On 2025/6/13 上午9:31, Xianglai Li wrote:
Add the acpi table to the loongson rtc hardware
so that the virtual machine kernel can use the
loongson RTC-related drivers.
Signed-off-by: Xianglai Li
---
Cc: Bibo Mao
Cc: Song Gao
Cc: Jiaxun Yang
Cc: Xianglai Li
hw/loongarch/virt-acpi-build.c
: Bibo Mao
Cc: Song Gao
Cc: Jiaxun Yang
Cc: Xianglai Li
hw/loongarch/virt-fdt-build.c | 11 +--
hw/rtc/ls7a_rtc.c | 26 +-
2 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/hw/loongarch/virt-fdt-build.c b/hw/loongarch/virt-fdt-build.c
split into two patches, one is fixup with irq pulse
type setting, the other is fixup with expired time out calculation in
rtc emulation driver.
Regards
Bibo Mao
Timer interrupts are sent using pulse functions.
Signed-off-by: Xianglai Li
---
Cc: Bibo Mao
Cc: Song Gao
Cc: Jiaxun Yang
Cc
: Xianglai Li
---
Cc: Bibo Mao
Cc: Song Gao
Cc: Jiaxun Yang
Cc: Xianglai Li
hw/loongarch/virt-acpi-build.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c
index 2cd2d9d842..2cfc5421c5 100644
--- a/hw
requirement with virtio-blk-pci with test case.
4. Merge patch 6 and patch 3 into together, and adjust patch order.
5. Add oem-id test case.
---
Bibo Mao (5):
tests/acpi: Add empty ACPI data files for LoongArch
tests/qtest/bios-tables-test: Add basic testing for LoongArch
rebuild-expected
The acpi table data is filled for LoongArch virt machine with the
following command:
tests/data/acpi/rebuild-expected-aml.sh
Signed-off-by: Bibo Mao
---
tests/data/acpi/loongarch64/virt/APIC | Bin 0 -> 108 bytes
tests/data/acpi/loongarch64/virt/APIC.topology | Bin 0 -> 153
Add basic ACPI table test case for LoongArch, including cpu topology,
numa memory, memory hotplug and oem-id test cases.
Signed-off-by: Bibo Mao
---
tests/qtest/bios-tables-test.c | 79 ++
tests/qtest/meson.build| 1 +
2 files changed, 80 insertions
Update the list of supported architectures to include LoongArch.
Signed-off-by: Bibo Mao
---
tests/data/acpi/rebuild-expected-aml.sh | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/data/acpi/rebuild-expected-aml.sh
b/tests/data/acpi/rebuild-expected-aml.sh
index
Remove stale allowed tables for LoongArch virt machine.
Signed-off-by: Bibo Mao
---
tests/qtest/bios-tables-test-allowed-diff.h | 8
1 file changed, 8 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index bad1380eec
Add empty acpi table for LoongArch virt machine, it is only empty
file and there is no data in these files.
Signed-off-by: Bibo Mao
---
tests/data/acpi/loongarch64/virt/APIC | 0
tests/data/acpi/loongarch64/virt/DSDT | 0
tests/data/acpi/loongarch64/virt/FACP | 0
tests/data
vec default */
-ret |= BIT_ULL(IOCSRM_AVEC_EN);
+if (virt_is_avecintc_enabled(lvms)) {
+ret |= BIT_ULL(IOCSRM_AVEC_EN);
+}
Is it really that reading of MISC_FUNC_REG will return
BIT_ULL(IOCSRM_AVEC_EN) if there is avec?
Where is the write operation with re
RS; irq++) {
+qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[irq], 1);
+}
One parent irqline for per-cpu is ok, so the total number of parent
irqline is s->num_cpu, the number of possible cpu.
+}
+qdev_init_gpio_in(dev, avec_irq_handler, NR_VECTORS * s-
_LOW)
for pch_msi is
[VIRT_PCH_MSI_ADDR_LOW, VIRT_PCH_MSI_ADDR_LOW + 0x8)
For parent line, AVEC is connected to CPU MSGINT BIT14 and pch_msi is
connected to extioi.
So they can coexists together, it only depends on how guest kernel use
MSI controller.
Regards
Bibo Mao
+
aque, int irq, int level)
{
-return;
+int cpu_num, irq_num = 0;
+LoongArchAVECState *s = LOONGARCH_AVEC(opaque);
+cpu_num = irq / 256;
+irq_num = irq % 256;
+
+avec_set_irq(s, cpu_num, irq_num, level);
}
When is the function avec_irq_handler() called?
Regards
Bibo Mao
static void loongarch_avec_realize(DeviceState *dev, Error **errp)
4(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 0);
+ env->CSR_MSGIR = FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, ACTIVE, 1);
+ return;
+}
what is the use about else {} sentences? Does it change interrupt logic
if AVEC is disabled?
Also I think it should be removed to the followin
(CSR_ESTAT, IS, 0, 13)
-FIELD(CSR_ESTAT, MSGINT, 14, 1)
+FIELD(CSR_ESTAT, MSGINT, 14, 1)/* used for msg */
ditto, how about modify IS such as FIELD(CSR_ESTAT, IS, 0, 15)?
Regards
Bibo Mao
FIELD(CSR_ESTAT, ECODE, 16, 6)
FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
diff --git a/target/loongarch/cpu.c b
If kvm_irqchip_in_kernel() return true, interrupt controller
ExtIOI, IPI, PCH_PCI and PCH_MSI should be emlated in kernel. And
it is not necessary to create memory region for these devices in
user space.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c| 57
Register IOCSR MISC_FUNC_REG is to enable features about EXTIOI
irqchip. If EXTIOI is emulated in kernel, MISC_FUNC_REG register
should be emulated in kernel also.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/loongarch/virt.c b
Option kernel_irqchip=split is not supported on LoongArch virt machine,
report error and exit if detect split kernel_irqchip option.
Signed-off-by: Bibo Mao
---
target/loongarch/kvm/kvm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/kvm/kvm.c b
to reload register
state.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 4
hw/intc/loongarch_extioi_kvm.c | 4
hw/intc/loongarch_ipi.c| 4
hw/intc/loongarch_ipi_kvm.c| 4
hw/intc/loongarch_pch_pic.c| 4
hw/intc/loongarch_pic_kvm.c| 4
If kvm_irqchip_in_kernel() return true, MSI interrupt can be injected
with API kvm_irqchip_send_msi() to KVM.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_msi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
index
If kvm_irqchip_in_kernel() return true, irq line interrupt can be
injected with API kvm_set_irq() to KVM.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
index 4d232f4cca
Add save and store funtction if kvm_irqchip_in_kernel() return true,
it is to get and set ExtIOI irqchip state from KVM kernel.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 14 +
hw/intc/loongarch_extioi_kvm.c | 90 ++
include/hw/intc
Add pre_save and post_load interfaces with ipi_common class, here only
framework ipi_common adds these interfaces. The defailed implementation
is LoongArchIPI child device in later.
Signed-off-by: Bibo Mao
---
hw/intc/loongson_ipi_common.c | 28 +++
include/hw
Function kvm_extioi_realize() is added if kvm_irqchip_in_kernel is
set. It is to create and initialize ExtIOI device in kernel mode.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 31
hw/intc/loongarch_extioi_kvm.c | 46
Add save and store funtction if kvm_irqchip_in_kernel() return true,
it is to get and set PCH PCI irqchip state from KVM kernel.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c| 22
hw/intc/loongarch_pic_kvm.c| 47 ++
include
Function kvm_pic_realize() is added if kvm_irqchip_in_kernel() return true.
It is to notify KVM kernel to create and initialize PCH PCI device in
kernel mode.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 14 ---
hw/intc/loongarch_pic_kvm.c | 38
Add save and store funtction if kvm_irqchip_in_kernel() return true,
it is to get and set IPI irqchip state from KVM kernel.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 20
hw/intc/loongarch_ipi_kvm.c | 54 +
include/hw/intc
Function kvm_ipi_realize() is added if kvm_irqchip_in_kernel() return true.
It is to create and initialize IPI device in kernel mode.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 5 +
hw/intc/loongarch_ipi_kvm.c | 27 +++
hw/intc
irqchip is
set since it access EXTIOI memory region, this register need be
emulated in kernel.
Bibo Mao (13):
hw/intc/loongarch_extioi: Add kernel irqchip realize function
hw/intc/loongarch_extioi: Add kernel irqchip save and restore function
hw/intc/loongarch_ipi: Add kernel irqchip
Interrupt controller extioi supports 256 vectors, register EXTIOI_COREISR
records pending interrupt status with bitmap method. Size of EXTIOI_COREISR
is 256 / 8 = 0x20 bytes, EXTIOI_COREISR_END should be EXTIOI_COREISR_START
+ 0x20 rather than 0xB20.
Signed-off-by: Bibo Mao
---
include/hw/intc
On big endian host machine such as S390, bios-table-test fails to run.
And also linux kernel fails to boot.
This patches solves these two issues.
Bibo Mao (2):
hw/loongarch/virt: Fix big endian support with MCFG table
hw/intc/loongarch_pch: Convert to little endian with ID register
hw/intc
machine S390.
Fixes: 735143f10d3e ("hw/loongarch: Add acpi ged support")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Bibo Mao
---
hw/loongarch/virt-acpi-build.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-ac
hine with TCG method.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
index cbba2fc284..ebb33ed0b0 100644
--- a/hw/intc/loongarch_pch_pic.c
+++ b/hw/intc/loonga
Identical Implementation : 0
I'm sending a pull request later today. Once merged, pls
rebase on top of that, updating loongarch as appropriate
and repost copying relevant people.
Cc Bibo Mao for more insight.
Hi Micheal,
I am trying to reproduce this issue. I have applied the
patchset
Song,
It is a little strange that patch with three version is sent in one day.
Maybe we should keep careful and calm :-)
Regards
Bibo Mao
On 2025/6/3 下午4:25, Song Gao wrote:
on qemu we got an aborted error
**
ERROR:../target/loongarch/tcg/insn_trans/trans_vec.c.inc:3574:vldi_get_value:
code
Reviewed-by: Bibo Mao
On 2025/6/3 上午11:18, Qiang Ma wrote:
Commit bab27ea2e3 ("hw/arm/virt: smbios:
inform guest of kvm") fixes the same issue
on arm.
without this patch:
[root@localhost ~]# virt-what
qemu
with this patch:
[root@localhost ~]# virt-what
kvm
Signed-off-by: Qiang Ma
is the one you published and 3e82ddaa8d is the
qemu.git/master.
I could not figure it out. Must be a loongarch bug dealing
with s390 hosts. I dropped them from the tag for now.
Cc contributor to figure it out.
Bibo Mao pls take a look.
New tag:
0b006153b7ec66505cb2d231235aa19ca5d2ce37
Thanks!
If kvm_irqchip_in_kernel() return true, interrupt controller
ExtIOI, IPI, PCH_PCI and PCH_MSI should be emlated in kernel. And
it is not necessary to create memory region for these devices in
user space.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c| 57
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