Not all pmem regions are backed by non-volatile memory. Syncing volatile
memory provides no benefit, but can cause performance issues is some
cases. Only sync memory that is marked as non-volatile.
Signed-off-by: Ben Chaney
Fixes: bd108a44bc29 (migration: ram: Switch to ram block writeback
On 6/16/25, 4:35 PM, "Peter Xu" mailto:pet...@redhat.com>>
wrote:
> On Mon, Jun 16, 2025 at 07:43:02PM +, Chaney, Ben wrote:
>> Not all pmem regions are backed by non-volatile memory. Syncing volatile
>> memory provides no benefit, but can cause performanc
Not all pmem regions are backed by non-volatile memory. Syncing volatile
memory provides no benefit, but can cause performance issues is some
cases. Only sync memory that is marked as non-volatile.
Fixes: bd108a44bc29 (migration: ram: Switch to ram block writeback)
---
migration/ram.c | 4 +++-
1
ill not
>lose if power is off.
Thank you for clarifying. I think I initially misunderstood the purpose of
this code path.
In that case, how about something like this to restrict the sync to only
run when it would be effective? If the memory region is volatile then
there is no benefit to s
Change to using TYPE_RISCV_CPU_CVA6 once this is merged.
Signed-off-by: Ben Dooks
---
hw/riscv/cva6.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/riscv/cva6.c b/hw/riscv/cva6.c
index 3adfa8b5cc..e6fd0ebafc 100644
--- a/hw/riscv/cva6.c
+++ b/hw/riscv/cva6.c
@@ -83,8
Add the CVA6 (the corev_apu from the fpga) model from
https://github.com/openhwgroup/cva6
Tree at:
https://gitlab.com/CodethinkLabs/qemu/-/tree/bjdooks/cva6-send-8jun2025?ref_type=heads
Fixes:
v3:
- fix missing file source
- set 64bit only for now
v2:
- rebased and fixed whitespace issues
Add a (currently Genesy2 based) CVA6 machine.
Has SPI and UART, the GPIO and Ethernet are currently black-holed
as there is no hardware model for them (lowRISC ethernet and Xilinx
GPIO)
Signed-off-by: Ben Dooks
---
v3:
- fix missed plic comment
- made 64bit only for now
v2:
- whitespace fixes
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05eb393..3daf75568c 100644
--- a/target/riscv
On 09/06/2025 12:30, Daniel Henrique Barboza wrote:
On 6/9/25 7:40 AM, Ben Dooks wrote:
On 07/06/2025 21:17, Daniel Henrique Barboza wrote:
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks
---
The README states right at the start
On 09/06/2025 12:30, Daniel Henrique Barboza wrote:
On 6/9/25 7:40 AM, Ben Dooks wrote:
On 07/06/2025 21:17, Daniel Henrique Barboza wrote:
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks
---
target/riscv/cpu-qom.h | 1
On 09/06/2025 12:24, Daniel Henrique Barboza wrote:
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add a (currently Genesy2 based) CVA6 machine.
Has SPI and UART, the GPIO and Ethernet are currently black-holed
as there is no hardware model for them (lowRISC ethernet and Xilinx
GPIO)
Signed-off-by
On 07/06/2025 21:17, Daniel Henrique Barboza wrote:
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/target
Add a (currently Genesy2 based) CVA6 machine.
Has SPI and UART, the GPIO and Ethernet are currently black-holed
as there is no hardware model for them (lowRISC ethernet and Xilinx
GPIO)
Signed-off-by: Ben Dooks
---
v2:
- whitespace fixes
- use g_autofree on plic
v1:
- squashed in fixes for sd
This implements the CVA6 (the corev_apu from the fpga) model.
v2:
- fixed whitespace and rebased patches
On 26/05/2025 11:10, Daniel Henrique Barboza wrote:
On 5/21/25 12:54 PM, Ben Dooks wrote:
Add a (currently Genesy2 based) CVA6 machine.
Has SPI and UART, the GPIO and Ethernet are currently black-holed
as there is no hardware model for them (lowRISC ethernet and Xilinx
GPIO)
Signed-off-by
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05eb393..3daf75568c 100644
--- a/target/riscv
Change to using TYPE_RISCV_CPU_CVA6 once this is merged.
Signed-off-by: Ben Dooks
---
hw/riscv/cva6.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/riscv/cva6.c b/hw/riscv/cva6.c
index 3adfa8b5cc..e6fd0ebafc 100644
--- a/hw/riscv/cva6.c
+++ b/hw/riscv/cva6.c
@@ -83,8
This is an addition of the CVA6 (as implemented by the
corev_apu) that we've been working on.
Min arguments -M cva6 -m 1G -sd -bios
both read and write, any other OP code is deemed invalid and
will abort the transfer.
todo:
- add proper vmstate helper for users
- get implementation fully tested with lowrisc_eth
Signed-off-by: Ben Dooks
---
notes:
- squashed in tracing and fixups
---
hw/net/Kconfig | 3 +
h
Add initial implementation of PHY via bit-banged code.
This is to test the mdio_bb code and will need updating
for real board values.
---
hw/net/Kconfig | 1 +
hw/net/lowrisc.c | 42 +++-
include/hw/net/lowrisc_eth.h | 4
3 files ch
This is a model for the lowrisc_ethernet block, a simple
network driver found in the CVA6 CoreV APU.
Signed-off-by: Ben Dooks
---
note, squashed in "hw/net: lowrisc cleanups"
---
hw/net/Kconfig | 3 +
hw/net/lowrisc.c | 474 +
As part of the CVA6 project we're working on we did an
ethernet implementation as part of adding a machine to
emulate the FPGA build.
As part of this, we've done an MDIO bit-bang decoder
which might be useful (although we can get by with
just the ethernet MAC part)
Add a (currently Genesy2 based) CVA6 machine.
Has SPI and UART, the GPIO and Ethernet are currently black-holed
as there is no hardware model for them (lowRISC ethernet and Xilinx
GPIO)
Signed-off-by: Ben Dooks
---
- squashed in fixes for sd-card and new qemu init
- move to spdx for cva6
Add CVA6 CPU type, for the OpenHW CVA6 cores
Signed-off-by: Ben Dooks
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 19 +++
2 files changed, 20 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 4cfdb74891..b5460771d7 100644
--- a
On 5/13/25, 1:21 PM, "David Hildenbrand" mailto:da...@redhat.com>> wrote:
> Are you using a read-only NVDIMM?
> In that case, I assume we would never need msync.
We aren't using an NVDIMM at all, we are using pmem that is backed by DRAM.
Ben
on? Is it since v10.0 release?
Hi Peter,
We are still on an old branch (7.2). The issue began when we enabled
pmem, not as the result of a code change.
Thanks,
Ben
letes, the
guest can redirty the pages. If the host crashes after that point, the guest
memory will still be in an inconsistent state unless the crash is exceptionally
well timed. Does anyone have any insight into why this sync operation was
introduced?
Thank you,
Ben Chaney
-by: Ben Dooks
[1] https://mail.gnu.org/archive/html/qemu-devel/2025-04/msg03982.html
---
target/riscv/cpu.h| 2 +-
target/riscv/cpu_helper.c | 7 +--
target/riscv/translate.c | 5 -
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/ri
On 23/04/2025 14:08, Paolo Bonzini wrote:
On 4/23/25 12:09, Ben Dooks wrote:
In adding a new feature to the riscv target, it turns out the
tb_flags had already got to the 32-bit limit. Everyone other target
has been fine with uint32_t (except perhaps arm which does somethng
strange to extend
On 23/04/2025 11:09, Ben Dooks wrote:
In adding a new feature to the riscv target, it turns out the tb_flags
had already got to the 32-bit limit. Everyone other target has been
fine with uint32_t (except perhaps arm which does somethng strange to
extend tb_flags, I think).
To allow extending of
/cpu.h#L666 adding PM_SIGNEXTEND where we had BE_DATA)
Q: Do the cpu_get_tb_state calls need uint32_t changing to the
tb_flag_t as part of this?
Q: As part of this, should we also define a FLAG_DP_TB or similar
wrapper for the relevant change?
Signed-off-by: Ben Dooks
---
accel/tcg/cpu-exec.c
c": "Failed to connect to 'cpr.sock':
Permission denied"}}
I provided a minimal patch that works around the second issue.
Thank you,
Ben Chaney
---
include/system/os-posix.h | 4
os-posix.c | 8
util/qemu-sockets.c | 21 +
3 files changed, 2
quot;addr": { "transport": "socket", "type":
"unix",
"path": "/opt/bchaney-tmp/main.sock"}},
{"channel-type": "cpr",
"addr": { "transport": "socket", "type": "unix",
"path": "/opt/bchaney-tmp/cpr.sock"}}]}}
{"execute": "query-status"}
Is this a hardware configuration that is currently intended to be supported? If
not, will it be supported in the future?
Thank you,
Ben Chaney
On 2024-10-07 18:17, Titus Rwantare wrote:
This patch adds the quanta-gsz-bmc target, a current Google machine of
the day. This machine will be used as a platform to enable features
such
as the PECI bmc interface, and Intel eSPI virtual wire interface in
QEMU.
Signed-off-by: Titus Rwantare
If you create a new timer before the timer lists have been
initialised then you will end up with an abort due to trying
to access an illegal timer list struct. Add an assert() for
the timer list being NON-null.
Signed-off-by: Ben Dooks
---
util/qemu-timer.c | 1 +
1 file changed, 1 insertion
TU windows (see patch
https://lists.gnu.org/archive/html/qemu-devel/2023-12/msg02643.html)
Hmm, thought I had fixed this a while ago when doing some work
with another systems and 64bit PCIe support as well.
--
Ben Dooks http://www.codethink.co.uk/
2]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00737.html
Signed-off-by: Ben Dooks
Suggested-by: Peter Maydell
---
v2:
- fixes as suggested by Peter Maydell to include icv_fullprio_mask()
---
hw/intc/arm_gicv3_cpuif.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On 14/11/2023 17:14, Peter Maydell wrote:
On Tue, 14 Nov 2023 at 16:54, Ben Dooks wrote:
The ICC_PMR_ELx bit msak returned from icc_fullprio_mask
should technically also remove any bit above 7 as these
are marked reserved (read 0) and should therefore should
not be written as anything other
The ICC_PMR_ELx bit msak returned from icc_fullprio_mask
should technically also remove any bit above 7 as these
are marked reserved (read 0) and should therefore should
not be written as anything other than 0.
Signed-off-by: Ben Dooks
---
hw/intc/arm_gicv3_cpuif.c | 2 +-
1 file changed, 1
Hi, is there an git tree with this series or a newer one available
please?
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
bits:
-cpu rv64,asid-bits=8
or no asids:
-cpu rv64,asid-bits=0
Signed-off-by: Ben Dooks
---
target/riscv/cpu.c | 42 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 2 ++
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c
ude/hw/i3c/aspeed_i3c.h
> create mode 100644 include/hw/i3c/i3c.h
> create mode 100644 include/hw/i3c/mock-target.h
> create mode 100644 include/hw/i3c/remote-i3c.h
> delete mode 100644 include/hw/misc/aspeed_i3c.h
> create mode 100644 tests/qtest/remote-i3c-test.c
>
> --
> 2.40.0.348.gf938b09366-goog
>
>
--
Ben Dooks, b...@fluff.org, http://www.fluff.org/ben/
Large Hadron Colada: A large Pina Colada that makes the universe disappear.
On 17/03/2023 14:11, Pavel Pisa wrote:
Hello Ben,
thanks for update.
On Thursday 16 of March 2023 13:41:13 Ben Dooks wrote:
From: Ben Dooks
Add support for Microchip MCP25625 SPI based CAN controller which is
very similar to the MCP2515 (and covered by the same Linux driver).
This can be
From: Ben Dooks
Add support for Microchip MCP25625 SPI based CAN controller which is
very similar to the MCP2515 (and covered by the same Linux driver).
This can be added to any machine with SPI support in the machine
model file.
Example for using this when configured into a machine
On Tue, Jan 17, 2023 at 07:16:35PM +0100, Pavel Pisa wrote:
> Dear Ben,
>
> sorry for longer response times...
I think we've both dropped the ball on this one, just got reminded about
this set and found it got deleted from work email.
We've done review upates and will try an
, "riscv");
qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
You'll need the same for riscv,cboz-block-size as well.
--
Ben Dooks
de
runner resources to help?
--
Ben Dooks, b...@fluff.org, http://www.fluff.org/ben/
Large Hadron Colada: A large Pina Colada that makes the universe disappear.
On 04/01/2023 12:22, Ben Dooks wrote:
From: Ben Dooks
Add support for Microchip MCP25625 SPI based CAN controller which is
very similar to the MCP2515 (and covered by the same Linux driver).
This can be added to any machine with SPI support in the machine
model file.
Example for using this
On 04/01/2023 12:22, Ben Dooks wrote:
From: Ben Dooks
Add support for Microchip MCP25625 SPI based CAN controller which is
very similar to the MCP2515 (and covered by the same Linux driver).
This can be added to any machine with SPI support in the machine
model file.
Example for using this
From: Ben Dooks
Add support for Microchip MCP25625 SPI based CAN controller which is
very similar to the MCP2515 (and covered by the same Linux driver).
This can be added to any machine with SPI support in the machine
model file.
Example for using this when configured into a machine
> >
> > Cc: Michael Walle
> > Cc: Tudor Ambarus
> > Signed-off-by: Guenter Roeck
>
> Reviewed-by: Cédric Le Goater
If SFDP is a standard, couldn't we have an function to generate it from
the flash parameters?
--
Ben Dooks, b...@fluff.org, http://www.fluff
On 21/10/2022 08:00, Andrew Jones wrote:
On Fri, Oct 21, 2022 at 06:58:02AM +0100, Ben Dooks wrote:
Add a qemu_fdt_setprop_strings to set a string array into a device-tree.
Only minor updates from v4 to fix a couple of minor patch issues.
Please see the comments I made on patch 1 of the v4
Change to using the qemu_fdt_setprop_strings() helper in
hw/core code.
Signed-off-by: Ben Dooks
---
hw/core/guest-loader.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c
index c61ebc4144..7b8e32e06f 100644
--- a
/guest-loader.c is the only place where an
return is checked).
Signed-off-by: Ben Dooks
---
hw/core/guest-loader.c | 22 +++---
1 file changed, 7 insertions(+), 15 deletions(-)
diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c
index 391c875a29..c61ebc4144 100644
--- a/hw
Add a qemu_fdt_setprop_strings to set a string array into a device-tree.
Only minor updates from v4 to fix a couple of minor patch issues.
Change to using qemu_fdt_setprop_strings() instead of using
\0 separated string arrays. Note, also there were a few places
where qemu_fdt_setprop_string() can be used in the same areas.
Signed-off-by: Ben Dooks
---
v4:
- fixed checkpatch errors with string
- fixed patch subject
---
hw/arm
Change to using qemu_fdt_setprop_strings() helper in hw/mips.
Signed-off-by: Ben Dooks
Reviewed-by: Peter Maydell
---
hw/mips/boston.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index d2ab9da1a0..759f6daafe 100644
--- a/hw
Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify the code.
Signed-off-by: Ben Dooks
---
v5: fix re-ordering in sifive_u
---
hw/riscv/sifive_u.c | 18 +-
hw/riscv/spike.c| 7 ++-
hw/riscv/virt.c | 25 ++---
3 files changed, 13
r **)&clint_compat, ARRAY_SIZE(clint_compat));
Signed-off-by: Ben Dooks
---
v4:
- go back to the non-return call, no-one is using the result
v3;
- fix return value for the call
- add better help text
v2:
- fix node/path in comment
---
include/sysemu/device_tree.h | 19 +++
1 file cha
Ie Capabilities and
> Extended Capabilities requires this to be used to uniquely
> identify CXL memory devices.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
> ---
>
> This is the missing element to be able to use the Linux kernel
> support for PMEM region
Change to using qemu_fdt_setprop_strings() instead of using
\0 separated string arrays. Note, also there were a few places
where qemu_fdt_setprop_string() can be used in the same areas.
Signed-off-by: Ben Dooks
---
v4:
- fixed checkpatch errors with string
- fixed patch subject
---
hw/arm
Change to using the qemu_fdt_setprop_strings() helper in
hw/core code.
Signed-off-by: Ben Dooks
---
hw/core/guest-loader.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c
index c61ebc4144..7b8e32e06f 100644
--- a
On Tue, Aug 09, 2022 at 07:56:34PM +0100, Ben Dooks wrote:
> Add a helper for qemu_fdt_setprop_strings() to take a set of strings
> to put into a device-tree, which removes several open-coded methods
> such as setting an char arr[] = {..} or setting char val[] = "str\0str2";
r **)&clint_compat, ARRAY_SIZE(clint_compat));
Signed-off-by: Ben Dooks
---
v4:
- go back to the non-return call, no-one is using the result
v3;
- fix return value for the call
- add better help text
v2:
- fix node/path in comment
---
include/sysemu/device_tree.h | 19 +++
1 file cha
/guest-loader.c is the only place where an
return is checked).
Signed-off-by: Ben Dooks
---
hw/core/guest-loader.c | 22 +++---
1 file changed, 7 insertions(+), 15 deletions(-)
diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c
index 391c875a29..c61ebc4144 100644
--- a/hw
Add a helper for qemu_fdt_setprop_strings() to take a set of strings
to put into a device-tree, which removes several open-coded methods
such as setting an char arr[] = {..} or setting char val[] = "str\0str2";
This is for hw/arm, hw/mips and hw/riscv as well as a couple of cores. It
is not
Change to using qemu_fdt_setprop_strings() helper in hw/mips.
Signed-off-by: Ben Dooks
Reviewed-by: Peter Maydell
---
hw/mips/boston.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index d2ab9da1a0..759f6daafe 100644
--- a/hw
Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify the code.
Signed-off-by: Ben Dooks
---
hw/riscv/sifive_u.c | 18 +-
hw/riscv/spike.c| 7 ++-
hw/riscv/virt.c | 32
3 files changed, 15 insertions(+), 42 deletions(-)
diff
On Mon, Aug 01, 2022 at 12:30:22PM +0100, Peter Maydell wrote:
> On Wed, 27 Jul 2022 at 23:39, Ben Dooks wrote:
> >
> > Change to using the qemu_fdt_setprop_strings() helper in
> > hw/core code.
> >
> > Signed-off-by: Ben Dooks
> > ---
>
> Reviewed-
On Mon, Aug 01, 2022 at 12:37:33PM +0100, Peter Maydell wrote:
> On Wed, 27 Jul 2022 at 23:44, Ben Dooks wrote:
> >
> > Change to using qemu_fdt_setprop_strings() instead of using
> > \0 separated string arrays.
> >
> > Signed-off-by: Ben Dooks
> >
;
}
+static RISCVException sstc(CPURISCVState *env, int csrno)
+{
+CPUState *cs = env_cpu(env);
+RISCVCPU *cpu = RISCV_CPU(cs);
+
+if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+if (env->priv == PRV_M) {
+ return R
On Thu, Jul 28, 2022 at 11:22:27AM +0200, Andrew Jones wrote:
> On Wed, Jul 27, 2022 at 11:39:01PM +0100, Ben Dooks wrote:
> > Add a helper to set a property from a set of strings
> > to reduce the following code:
> >
> > static const char * const clint_compat
p; has_ext(ctx, RVS))
{\eventually
meaning
+stateen &= sstateen; \
+} \
+if (!(stateen & SMSTATEEN0_FCSR)) { \
+return false; \
+} \
+} \
given the size of that I would have thought an "static inline"
function would be easier to write and maintai
On Wed, Jul 27, 2022 at 11:39:00PM +0100, Ben Dooks wrote:
> Add a helper for qemu_fdt_setprop_strings() to take a set of strings
> to put into a device-tree, which removes several open-coded methods
> such as setting an char arr[] = {..} or setting char val[] = "str\0str2";
Change to using qemu_fdt_setprop_strings() helper in hw/mips.
Signed-off-by: Ben Dooks
---
hw/mips/boston.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index d2ab9da1a0..759f6daafe 100644
--- a/hw/mips/boston.c
+++ b/hw/mips
Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify the code.
Signed-off-by: Ben Dooks
---
hw/riscv/sifive_u.c | 18 +-
hw/riscv/spike.c| 7 ++-
hw/riscv/virt.c | 32
3 files changed, 15 insertions(+), 42 deletions(-)
diff
Add a helper for qemu_fdt_setprop_strings() to take a set of strings
to put into a device-tree, which removes several open-coded methods
such as setting an char arr[] = {..} or setting char val[] = "str\0str2";
This is for hw/arm, hw/mips and hw/riscv as well as a couple of cores. It
is not fully
r **)&clint_compat, ARRAY_SIZE(clint_compat));
Signed-off-by: Ben Dooks
---
v3;
- fix return value for the call
- add better help text
v2:
- fix node/path in comment
---
include/sysemu/device_tree.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/sysemu/device_tre
Change to using qemu_fdt_setprop_strings() instead of using
\0 separated string arrays.
Signed-off-by: Ben Dooks
---
hw/arm/boot.c | 8 +++---
hw/arm/virt.c | 28 +
hw/arm/xlnx-versal-virt.c | 51 ---
3 files
Change to using the qemu_fdt_setprop_strings() helper in
hw/core code.
Signed-off-by: Ben Dooks
---
hw/core/guest-loader.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c
index 391c875a29..203090503e 100644
--- a
On 27/07/2022 15:38, Bin Meng wrote:
On Wed, Jul 27, 2022 at 10:24 PM Ben Dooks wrote:
Is anyone working on adding a sifive-u74 core to the list of supported
CPU types? I was looking at full emulation of the Unmatched but at the
moment the best we have is sifive-u54 and I think that misses at
at some point to add to the current real-board testing
we're doing.
(I have a basic addition of the type and the two CSRs as a couple of
patches if that would help as a start)
--
Ben Dooks, b...@fluff.org, http://www.fluff.org/ben/
Large Hadron Colada: A large Pina Colada that makes the universe disappear.
On 27/07/2022 13:56, Peter Maydell wrote:
On Wed, 27 Jul 2022 at 12:15, Ben Dooks wrote:
On Wed, Jul 13, 2022 at 05:54:42PM +0100, Ben Dooks wrote:
As part of a project we have been looking at using the DesignWare
PCIe host. We found a few issues of missing features or small bugs
when using
On 27/07/2022 13:56, Peter Maydell wrote:
On Wed, 27 Jul 2022 at 12:15, Ben Dooks wrote:
On Wed, Jul 13, 2022 at 05:54:42PM +0100, Ben Dooks wrote:
As part of a project we have been looking at using the DesignWare
PCIe host. We found a few issues of missing features or small bugs
when using
On Wed, Jul 13, 2022 at 05:54:42PM +0100, Ben Dooks wrote:
> As part of a project we have been looking at using the DesignWare
> PCIe host. We found a few issues of missing features or small bugs
> when using this with a recent Linux kernel (v5.17.x)
>
> Whilst doing this we also
ttps://lore.kernel.org/qemu-devel/20200902093107.608000-1-...@kaod.org/
Is there a git branch this could be pulled from to have a look at and
test on our setup?
--
Ben Dooks, b...@fluff.org, http://www.fluff.org/ben/
Large Hadron Colada: A large Pina Colada that makes the universe disappear.
On 18/07/2022 11:15, Peter Maydell wrote:
On Mon, 18 Jul 2022 at 11:05, Ben Dooks wrote:
On 13/07/2022 18:20, Ben Dooks wrote:
A model for the DesignWare GPIO (v1) block.
Is there anyone else who should be reviewing these that
was missed off the original list? I'd like to get an id
On 13/07/2022 18:20, Ben Dooks wrote:
A model for the DesignWare GPIO (v1) block.
Is there anyone else who should be reviewing these that
was missed off the original list? I'd like to get an idea
if there is any work to do. I've got a couple more drivers
to submit and was waiting o
On 13/07/2022 17:54, Ben Dooks wrote:
Versions 4 and above add support for 64-bit viewport
limit. Add support for the DESIGNWARE_PCIE_ATU_UPPER_LIMIT
regiser where supported.
Signed-off-by: Ben Dooks
Whoops, just noticed this was my old ct address.
---
hw/pci-host/designware.c
In version 4 and anver ATU CR1 has more bits in it than just the
viewport type. Make a guess at masking these out to avoid issues
where Linux writes these bits and fails to enable memory ATUs.
Signed-off-by: Ben Dooks
---
hw/pci-host/designware.c | 4 ++--
1 file changed, 2 insertions(+), 2
The driver should leave irq[0..3] for INT[A..D] but seems to put the
MSI IRQ at entry 3 which should also be INT_D. Extend the irqs[] array
to 5 entires and put the MSI at entry irqs[4].
Signed-off-by: Ben Dooks
---
hw/pci-host/designware.c | 2 +-
include/hw/pci-host/designware.h | 2
Versions 4 and above add support for 64-bit viewport
limit. Add support for the DESIGNWARE_PCIE_ATU_UPPER_LIMIT
regiser where supported.
Signed-off-by: Ben Dooks
---
hw/pci-host/designware.c | 22 +-
include/hw/pci-host/designware.h | 2 +-
2 files changed, 18
By inspection DESIGNWARE_PCIE_ATU_UPPER_TARGET should be writing to
the upper 32-bits of viewport->target, so fix this by shifting the
32-bit value before the or.
Signed-off-by: Ben Dooks
---
hw/pci-host/designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/
.
Signed-off-by: Ben Dooks
---
hw/pci-host/designware.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index d213d7324c..6403416634 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -345,6 +345,10 @@ static void
As part of a project we have been looking at using the DesignWare
PCIe host. We found a few issues of missing features or small bugs
when using this with a recent Linux kernel (v5.17.x)
Whilst doing this we also made a start on some tracing events.
This is a host to pcie bridge, so use PCI_CLASS_BRIDGE_HOST
for the class.
Signed-off-by: Ben Dooks
---
hw/pci-host/designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index b5d5b2b8a5..a47ae48071 100644
--- a/hw
Add a couple of tracing events for internal driver updates
Signed-off-by: Ben Dooks
---
hw/pci-host/designware.c | 4
hw/pci-host/trace-events | 4
2 files changed, 8 insertions(+)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index a47ae48071..489959513f 100644
A model for the DesignWare GPIO (v1) block.
Signed-off-by: Ben Dooks
---
hw/gpio/Kconfig | 3 +
hw/gpio/designware_gpio.c | 327 ++
hw/gpio/meson.build | 1 +
hw/gpio/trace-events | 7 +
include/hw/gpio
On Mon, Jun 20, 2022 at 04:47:44PM +1000, Alistair Francis wrote:
> On Sun, Jun 19, 2022 at 6:14 AM Ben Dooks wrote:
> >
> > Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify
> > the code.
> >
> > Signed-off-by: Ben Dooks
>
> Do you mind updatin
r **)&clint_compat, ARRAY_SIZE(clint_compat));
Signed-off-by: Ben Dooks
--
v2:
- fix node/path in comment
---
include/sysemu/device_tree.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h
index 79ce009a22..28b68bacaf 100644
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