Hi,
I'm looking into making NVME device "migratable".
Following previous discussion on
https://lists.gnu.org/archive/html/qemu-devel/2017-08/msg05091.html, I would
like to implement the VMStateDescription to save and restore the entire
controller state, including all the queues.
"NvmeCtrl" defi
I tested this with Intel tooling (Quartus Prime EDS) to build the nios2
firmware.
Shadow register set, EIC, VIC work as expected.
Looking forward to seeing this merged!
Thanks,
Amir
Something is wrong when translating rdprs in an interrupt handler when CRS is
0x1.
I'm hitting "../tcg/tcg.c:3466: tcg_reg_alloc_mov: Assertion `ts->val_type ==
TEMP_VAL_REG' failed."
When stopped on that assertion I can see that :
- ts->val_type = TEMP_VAL_DEAD
- op->opc = INDEX_op_mov_i32
- o
(Continue discussion from Re: [PATCH v4 24/33] target/nios2: Introduce shadow
register sets)
> > How does "cpu_crs_R" work?
> > ... Otherwise, each gpr access would be indirect. I'm probably missing
> > something here.
> They are indirect, but with some optimization.
Why not always access dire
Hi Richard,
How does "cpu_crs_R" work?
In your version you hold a pointer to the current register set instead of
copying registers back and forth like I did, which makes sense.
But how does TCG know which set to refer to when it generates code?
It looks like it's always accessing the same cpu_cr
ve defaults and depends)
- Added URL to VIC documentaion on Intel website
- Removed LOG_VIC
- Added comments in nios_vic.c
- Report an error in case of write to invalid CSR address
Changes from v1
===
- Splitted into several independant patches
- Added a board that wires up the VIC
Sig
Implement shadow register set and related instructions
rdprs, wrprs. Fix eret to update either status or sstatus
according to current register set.
eret also changes register set when needed.
Signed-off-by: Amir Gonnen
---
target/nios2/cpu.c | 1 +
target/nios2/cpu.h | 48
disable the internal interrupt controller, and the
devices on the machine are attached to the VIC (and not directly to cpu).
To allow VIC update EIC fields, we set the "cpu" property of the VIC
with a reference to the nios2 cpu.
Signed-off-by: Amir Gonnen
---
ned-off-by: Amir Gonnen
---
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/nios2_vic.c | 341
3 files changed, 345 insertions(+)
create mode 100644 hw/intc/nios2_vic.c
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 528e77b4a6..
.
rha, ril, rrs and rnmi are used when EIC handles external interrupt, in
order to decide if to take the interrupt now, which shadow register set
to use, which PC to jump to, whether to set NMI flag, etc.
Signed-off-by: Amir Gonnen
---
target/nios2/cpu.c| 54
eret instruction is only allowed in supervisor mode.
Signed-off-by: Amir Gonnen
---
target/nios2/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index ce3aacf59d..007c17e6e9 100644
--- a/target/nios2/translate.c
+++ b/target
> This looks wrong. Of course, so does nios2_cpu_set_irq, from which you've
> cribbed this.
> For our purposes, I think simply re-using env->regs[CR_IPENDING] as the
> external hw
> request word is the right thing to do. But we need to update RDCTL to
> compute the
> correct value from CR_IP
Hi Richard,
Thank you for your review and comments!
> You're missing a gen_check_supervisor here and in wrprs.
There's something I don't understand about gen_check_supervisor - it looks like
it checks CR_STATUS_U when generating code instead of generating code that
checks CR_STATUS_U.
Is that
Hi Peter,
> Is a VIC a configurable option on the real hardware (well, FPGA image, I
> guess) that this board is modelling ?
> I couldn't find any docs on it with a quick google.
This specific example-board from Intel does not provide a VIC option, as far as
I know.
(https://fpgacloud.intel.c
board that uses the VIC instead of the default internal interrupt
controller
Signed-off-by: Amir Gonnen
Amir Gonnen (4):
target/nios2: Shadow register set
target/nios2: Exteral Interrupt Controller (EIC)
hw/intc: Vectored Interrupt Controller (VIC)
hw/nios2: Machine with a Vectored
Implement shadow register set and related instructions
rdprs, wrprs. Fix eret to update either status or sstatus
according to current register set.
eret also changes register set when needed.
Signed-off-by: Amir Gonnen
---
target/nios2/cpu.c | 1 +
target/nios2/cpu.h | 47
.
rha, ril, rrs and rnmi are used when EIC handles external interrupt, in
order to decide if to take the interrupt now, which shadow register set
to use, which PC to jump to, whether to set NMI flag, etc.
Signed-off-by: Amir Gonnen
---
target/nios2/cpu.c | 58
ned-off-by: Amir Gonnen
---
hw/intc/Kconfig | 4 +
hw/intc/meson.build | 1 +
hw/intc/nios2_vic.c | 327
3 files changed, 332 insertions(+)
create mode 100644 hw/intc/nios2_vic.c
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 528e77b4a6..
disable the internal interrupt controller, and the
devices on the machine are attached to the VIC (and not directly to cpu).
To allow VIC update EIC fields, we set the "cpu" property of the VIC
with a reference to the nios2 cpu.
Signed-off-by: Amir Gonnen
---
n checkpatch.pl, etc.
Could you please point out where I failed to follow them or what I'm missing?
Thanks,
Amir
-Original Message-
From: Peter Maydell
Sent: Sunday, February 20, 2022 5:13 PM
To: Amir Gonnen
Cc: qemu-devel@nongnu.org; Chris Wulff ; Marek Vasut
Subject: Re: [PATC
>From 99efcd655e83f034bce25271fe592d8789529e54 Mon Sep 17 00:00:00 2001
From: Amir Gonnen
Date: Thu, 17 Feb 2022 15:43:14 +0200
Subject: [PATCH] target/nios2: Shadow register set, EIC and VIC
Implement nios2 Vectored Interrupt Controller (VIC).
This includes Exteral Interrupt Control
bal
state.
Thanks,
Amir
-Original Message-
From: Stefan Hajnoczi
Sent: Wednesday, December 15, 2021 11:46 AM
To: Amir Gonnen
Cc: qemu-devel@nongnu.org; peter.mayd...@linaro.org; f4...@amsat.org
Subject: Re: Building QEMU as a shared library
On Wed, Dec 15, 2021 at 08:18:53AM +, Am
Hi,
Before sending a patch, I would like to check if it's of interest to the
community.
My goal is to simulate a mixed architecture system.
Today QEMU strongly assumes that the simulated system is a *single
architecture*.
Changing this assumption and supporting mixed architecture in QEMU proved
** Description changed:
QEMU 3.0
block/sheepdog.c: In function 'find_vdi_name':
block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals
destination size [-Werror=stringop-truncation]
- strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN);
- ^~
Public bug reported:
QEMU 3.0
block/sheepdog.c: In function 'find_vdi_name':
block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals
destination size [-Werror=stringop-truncation]
strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN);
^
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