[Qemu-devel] Add proper alignment check and pending 'C' extension for riscv

Dear All, I'm submiting this patch to properly check the next instruction alignment and scheduale compression extenstion enable upon 'MISA' register writes to later aligned instruction through exporting next instruction 'pc' to riscv cpu state Thanks, Ahmed

[Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

From: ahmed_magdy Signed-off-by: ahmed_magdy --- target/riscv/cpu.h | 2 ++ target/riscv/csr.c | 5 +++-- target/riscv/translate.c | 14 ++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a269c07..b49bdb3 10