[PATCH] target/riscv: Fix the check with vector register multiples of LMUL

In the original extract32(val, 0, lmul) logic, when lmul is 2 and val is v10 or v12, there is an issue with this check condition. I think a simple mod operation is sufficient. Signed-off-by: Zhiwei Jiang --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH] tcg: Fix the overflow in indexing tcg_ctx->temps

2 3 fold_call (op=0x7f76fc0101f8, ctx=0x7f794bffe460) at ../tcg/optimize.c:1348 4 tcg_optimize (s=) at ../tcg/optimize.c:2369 5 0x7f7958ffa136 in tcg_gen_code (s=0x7f76fc000e00, tb=0x7f7904202380, pc_start=140741246462840) at ../tcg/tcg.c:6066 Signed-off-by: Zhiwei Jiang --- include/tcg/tcg.h

[PATCH] migration: RDMA registrations interval optimization

work as normal on my situation. Signed-off-by: Zhiwei Jiang --- migration/migration.c | 13 + migration/migration.h | 6 ++ migration/ram.c | 6 +- 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/migration/migration.c b/migration/migration.c index

[PATCH] block: fix build waring

); ^~~~ cc1: all warnings being treated as errors Signed-off-by: Zhiwei Jiang --- block.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block.c b/block.c index 3f456892d0..08f29e6b65 100644 --- a/block.c +++ b/block.c @@ -4866,7 +4866,7