Hi Aurelien,
I found that when qemu-system-mips64el executed 'movz' with -M mips, it
would raise a reserved instruction exception.
The mips spec describes movz as below:
Mnemonic Instructio Defined in MIPS ISA
MOVZMove Conditional on Zero MIPS3
Sorry for resend this mail, for I can't see it untill now, I thought I had
failed send to the mailist.
On Wed, Mar 7, 2012 at 3:35 PM, Andreas Färber wrote:
>
> How do you know? :)
>
I added a function in op_helper.c, then every insn will dump all the
registers when it runs. I traced the log and
Hi all,
I am working on adding a new target. Till now I have completed the cpu
part. I use it to run linux kernel. it can run to the end of linux kernel.
but there is no any message to the console.What should I do? Does timer and
pic must implement first? Should I implement a serial port?
thank you
HI All,
I am working on adding openrisc to qemu target. Till now I have done the
cpu part. I use it to run linux kernel. it can run to the end of linux
kernel. but there is no any message to the console.What should I do? Does
timer and pic must implement first? Need I implement a serial port or jus
On Tue, Jan 17, 2012 at 4:29 PM, Max Filippov wrote:
> > I'm adding a new target to qemu, now, I'm writing mmu simulation, but
> > it make me confused.
> >
> > When TLB miss occurred, I can't seperate DTLB miss from ITLB miss.
> >
> > I implemented it like this from target-xtensa:
> >
> > if (rw
Hi All,
I'm adding a new target to qemu, now, I'm writing mmu simulation, but
it make me confused.
When TLB miss occurred, I can't seperate DTLB miss from ITLB miss.
I implemented it like this from target-xtensa:
if (rw & 2)
HANDLE DTLB MISS
else
HANDLE ITLB MISS
But it didn't work. May
