> Reported-by: Alexandre Chartre
> Suggested-by: Daniel P. Berrangé
> Signed-off-by: Paolo Bonzini
> ---
> target/i386/kvm/kvm.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Good to see this fix. Late but,
Reviewed-by: Zhao Liu
| 10 +-
> hw/vfio/types.h | 21 +
> 2 files changed, 22 insertions(+), 9 deletions(-)
> create mode 100644 hw/vfio/types.h
Reviewed-by: Zhao Liu
2 files changed, 30 insertions(+), 30 deletions(-)
Reviewed-by: Zhao Liu
get/i386/host-cpu.h | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Zhao Liu
> This makes sense.
>
> In this case though, the next patch, a62fef5829956 "i386/cpu: Fix cpu
> number overflow in CPUID.01H.EBX[23:16]", becomes a one-liner:
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 2c9517f56d..5e55dd9ee5 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386
> Hi!
>
> Previous incarnation of this patch were Cc'd qemu-stable@, as it were
> supposed to be picked up for the stable qemu series. However, this
> incarnation is not Cc'd to stable, and, most importantly, it relies
> on a feature which was introduced after all released qemu versions.
> Namely
to
.instance_init")
Reported-by: Paolo Abeni
Tested-by: Paolo Abeni
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index da7d8dca633e..251d5760a0bd 100644
--- a/
On Wed, Jul 16, 2025 at 05:22:46PM +0200, Paolo Bonzini wrote:
> Date: Wed, 16 Jul 2025 17:22:46 +0200
> From: Paolo Bonzini
> Subject: Re: boot failure on top of current git
>
> On 7/16/25 16:44, Paolo Abeni wrote:
> > Hi,
> >
> > I'm observing boot failure for a rhel-9.7 VM. I'm using qemu git
r".
>
> v1:
> https://lore.kernel.org/qemu-devel/20250709104956.GAaG5JVO-74EF96hHO@fat_crate.local/
> ---
> target/i386/cpu.c | 2 +-
> target/i386/cpu.h | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Zhao Liu
> https://lore.kernel.org/qemu-devel/20250709104956.GAaG5JVO-74EF96hHO@fat_crate.local/
> ---
> target/i386/cpu.c | 17 +
> target/i386/cpu.h | 6 ++
> 2 files changed, 23 insertions(+)
Reviewed-by: Zhao Liu
On Mon, Jul 14, 2025 at 09:51:25AM -0500, Moger, Babu wrote:
> Date: Mon, 14 Jul 2025 09:51:25 -0500
> From: "Moger, Babu"
> Subject: Re: [PATCH v2 7/7] i386/cpu: Honor maximum value for
> CPUID.801DH.EAX[25:14]
>
> Hi Zhao,
>
> On 7/14/25 03:08, Zhao Liu
> > if (threads_per_pkg > 1) {
> > /*
> > - * Bits 15:12 is "The number of bits in the initial
> > - * Core::X86::Apic::ApicId[ApicId] value that indicate
> > - * thread ID within a package".
> > - * Bits 7:0 is "The number of
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes Since v1:
* Consider Zhaoxin CPU. (Ewan)
---
target/i386/cpu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8d67cadec2f2..37e4bf51d890 100644
--- a/target/i386/cpu.c
erflow in CPUID.01H.EBX[23:16]
i386/cpu: Fix overflow of cache topology fields in CPUID.04H
Zhao Liu (4):
i386/cpu: Mark EBX/ECX/EDX in CPUID 0x8000 leaf as reserved for
Intel
i386/cpu: Mark CPUID 0x8008 ECX bits[0:7] & [12:15] as reserved
for Intel/Zhaoxin
i386/cpu: Reor
Logical processor count". Current
result meets our expectation.
So round up CPUID.01H.EBX[23:16] to the nearest power-of-2 integer only
for Intel platform to solve the unexpected result.
Use the "x-vendor-cpuid-only-v2" compat option to fix this issue.
Reviewed-by: Zhao Liu
Signed-off-b
lue written to
EBX[23:16] to 255 as the HW does.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Xiaoyao Li
Signed-off-by: Qian Wen
Signed-off-by: Zhao Liu
---
Changes Since New v1 [**]:
* Rebase.
Changes Since Original v4 [*]:
* Rebase on addressable ID fixup.
* Drop R/b tags since the code base chan
Sort the CPUID leaves strictly by index to facilitate checking and
changing.
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 60 +++
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
to
describe CPU topology, which includes similar information, Intel and
Zhaoxin will not implement ECX bits[0:7] and bits[12:15] of 0x8008.
Therefore, mark these two fields as reserved and clear them for Intel
and Zhaoxin guests.
Reviewed-by: Tao Su
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
Signed-off-by: Zhao Liu
---
Changes Since New v1 [**]:
* Provide an overflow example of EAX[14:25].
Changes Since Original v4 [*]:
* Rebase on addressable ID fixup.
* Drop R/b tags since the code base changes.
* Teak bits 25-14 as well and add the comment.
* Fix overflow for host-cache-info
ned-off-by: Zhao Liu
---
Changes Since RFC v1 [*]:
* Correct the RFC's description, now there's the overflow case. Provide
an overflow example.
RFC:
* Although there are currently no overflow cases, to avoid any
potential issue, add the overflow check, just as I did for
Host YongFeng CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Ewan Hai
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes Since v1:
* New patch suggested by Ewan.
---
target/i386/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion
re.kernel.org/qemu-devel/ph0pr02mb738410511bf51b12db09be6cf6...@ph0pr02mb7384.namprd02.prod.outlook.com/
Signed-off-by: Manish Mishra
Co-authored-by: Xiaoyao Li
Signed-off-by: Xiaoyao Li
[Integrated and rebased 2 previous patches (ordered by post time)]
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Host GraniteRapids CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Igor Mammedov
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Rename the property to "x-force-cpuid-0x1f". (Igor)
---
t
complex cache indexing = false
number of sets (s) = 8192
(size synth) = 8388608 (8 MB)
--- cache 4 ---
cache type = no more caches (0)
Tested-by: Yi Lai
Signed-off-by: Ewan Hai
Signed-off-by: Zhao
Host SierraForest CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Igor Mammedov
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Rename the property to "x-force-cpuid-0x1f". (Igor)
---
target/
Host SapphireRapids CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Igor Mammedov
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Rename the property to "x-force-cpuid-0x1f". (Igor)
---
t
ned-off-by: Zhao Liu
---
target/i386/cpu.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4ce063fb6492..e9f3434b096c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2881,6 +2881,97 @@ st
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7f88fe0c8697..a97ee3c2af43 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2878,6 +2878,97 @@ st
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a97ee3c2af43..4ce063fb6492 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2881,6 +2881,97 @@ st
0401130205.2198253-34-xiaoyao...@intel.com/
Thanks and Best Regards,
Zhao
---
Ewan Hai (1):
i386/cpu: Introduce cache model for YongFeng
Manish Mishra (1):
i386/cpu: Add a "x-force-cpuid-0x1f" property
Zhao Liu (7):
i386/cpu: Introduce cache model for SierraForest
i386/cpu: Introdu
by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 43 ++-
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 34a82a378ccb..73872cb74b6f 100644
--- a/target/i386/cpu.c
+++
PUID 0x8005 leaf, in X86CPUState, a unified cache_info is
enough. It only needs to be initialized and configured with the
corresponding legacy cache model based on the vendor.
Cc: EwanHai
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Note, side effect of this patch: fix the inconsistency cache in
0x2 leaf. This
makes sense, as in the 0x2 leaf era, all supported caches should have
the corresponding descriptor.
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes Since v1:
* Fix the typo in comment. (Ewan)
---
target/
ate, a unified cache_info is
enough. It only needs to be initialized and configured with the
corresponding legacy cache model based on the vendor.
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 36 +++-
1 file changed, 31 insertions(+), 5 deletions(-)
compatibility later.
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 112 ++
1 file changed, 53 insertions(+), 59 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6cd942f95779..4a0505004bfb
ME of legacy_l2_cache_amd:
/*FIXME: CPUID leaf 0x8006 is inconsistent with leaves 2 & 4 */
In addition, per AMD's APM, update the comment of CPUID[0x8006].
[1]:
https://lore.kernel.org/qemu-devel/c522ebb5-04d5-49c6-9ad8-d755b8998...@zhaoxin.com/
Tested-by: Yi Lai
Signed-of
CPUs..
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes Since v1:
* Spilt this cleanup as a seperate patch.
---
target/i386/cpu.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6ab199c9a112..e0d5a39e477c
e the consistent
cache model, and use legacy_l2_cache as the default L2 cache.
Therefore, add descriptor 0x49 to represent general L2 cache.
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes Since v2:
* Fix the typo in comment. (Dapeng)
---
target/i386/cpu.c | 13 +++
ernal only, QEMU doesn't
support "internal" property. To avoid any other unexpected issues, check
the dependency.
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes Since v1:
* Split the x-vendor-cpuid-only-v2 support into a seperate pacth
and make sure it depends on x-v
",
"pentium", "pentium2" and "pentium3"), because they have already had the
special default cache model - legacy_intel_cpuid2_cache_info.
[1]:
https://lore.kernel.org/qemu-devel/5b31733c0709081227w3e5f1036odbc649edfdc8c...@mail.gmail.com/
[2]: https://lore.kernel.org/qemu-devel/478b65c8.
_info_amd
Note: patch 11-15 they each provide more specific evidence that
selecting a legacy cache model based on the Guest vendor in CPUID 0x2,
0x4, 0x8005, 0x80000006, and 0x801D leaves is both valid and
safe, and doesn't break compatibility.
Change Log
==
Changes Since v1:
* Add Tested-by & Reviewed-by.
* Addr
it is acceptable to select the default legacy cache model
based on the vendor.
For the CPUID 0x801D leaf, in X86CPUState, a unified cache_info is
enough. It only needs to be initialized and configured with the
corresponding legacy cache model based on the vendor.
Tested-by: Yi Lai
Signed-off-
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes Since v1:
* Drop lines_per_tag assertion in encode_cache_cpuid8005().
Changes Since RFC:
* Only set all-0 for Intel CPU.
* Add x-vendor-cpuid-only-v2.
---
target/i386/cpu.c | 12
1 file changed, 8 insertions(+), 4 dele
later.
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 101 +-
1 file changed, 54 insertions(+), 47 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 609efb10ddb5..6cd942f95779 100644
--- a
in X86CPUState, and during its initialization, set
different legacy cache models based on the vendor.
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 150 --
target/i386/cpu.h | 5 +-
2 files changed, 27
by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 47 +--
target/i386/cpu.h | 1 +
2 files changed, 38 insertions(+), 10 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4a0505004bfb..34a82a378ccb
Refer to SDM vol.3 table 1-21, add the notes about the missing
descriptor, and fix the typo and comment format.
Reviewed-by: Dapeng Mi
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
Changes Since v1:
* Fix the typo in comment. (Dapeng)
---
target/i386/cpu.c | 31
i Lai
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 31 +++
target/i386/cpu.h | 3 ++-
2 files changed, 13 insertions(+), 21 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 37cf591bea8d..af67f12e939d 100644
--- a/target/i386/cpu.c
+++ b/target
"pentium3") won't be used for migration, there's no need to add new
versioned CPU models
Tested-by: Yi Lai
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 65 +++
1 file changed, 65 insertions(+)
diff --git a/target/i386
ore.kernel.org/qemu-devel/afpocftpblb34...@intel.com/
> Signed-off-by: Paolo Bonzini
> ---
> target/i386/cpu.c | 8 ++++
> 1 file changed, 4 insertions(+), 4 deletions(-)
LGTM,
Reviewed-by: Zhao Liu
>
> Signed-off-by: Paolo Bonzini
> ---
> target/i386/cpu.c | 24
> target/i386/kvm/kvm-cpu.c | 2 ++
> 2 files changed, 14 insertions(+), 12 deletions(-)
Reviewed-by: Zhao Liu
On Fri, Jul 11, 2025 at 02:06:01AM +0200, Paolo Bonzini wrote:
> Date: Fri, 11 Jul 2025 02:06:01 +0200
> From: Paolo Bonzini
> Subject: [PATCH 2/4] target/i386: nvmm, whpx: add accel/CPU class that sets
> host vendor
> X-Mailer: git-send-email 2.50.0
>
> NVMM and WHPX are virtualizers, and there
-cpu.c | 3 ++-
> target/i386/kvm/kvm-cpu.c | 5 +++--
> 4 files changed, 9 insertions(+), 6 deletions(-)
Reviewed-by: Zhao Liu
gt; Reviewed-by: Eric Auger
> Signed-off-by: Shaoqin Huang
> ---
> hw/core/machine.c | 2 ++
> hw/display/ramfb-standalone.c | 2 +-
> hw/i386/microvm.c | 3 +++
> hw/i386/pc_piix.c | 10 ++
> hw/i386/pc_q35.c | 3 +++
> hw/vfio/pci.c | 2 +-
> 6 files changed, 20 insertions(+), 2 deletions(-)
Reviewed-by: Zhao Liu
gt; include/hw/display/ramfb.h| 2 +-
> 7 files changed, 13 insertions(+), 7 deletions(-)
LGTM,
Reviewed-by: Zhao Liu
On Thu, Jul 10, 2025 at 10:57:49AM +0800, Xiaoyao Li wrote:
> Date: Thu, 10 Jul 2025 10:57:49 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH] target/i386: Add TSA feature flags
[snip]
> > I recommend splitting this into two separate patches:
> > a. One patch to introduce the new bit 0021_EAX_VE
ouvier
> ---
> hw/core/null-machine.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Zhao Liu
et-info-qapi.h | 21 +
> include/qemu/target-info.h | 2 +-
> hw/core/machine-qmp-cmds.c | 8 +++-
> target-info.c | 8 ++++++++
> 4 files changed, 33 insertions(+), 6 deletions(-)
> create mode 100644 include/qemu/target-info-qapi.h
Reviewed-by: Zhao Liu
e cache level...
> +return true;
> + }
> +
...at least for now, this is fine for me. We can think of how to
organize everything better afterwards. So,
Reviewed-by: Zhao Liu
l allow bindgen to
> generate a bitflag using the enum variants as its domain of values.
>
> Signed-off-by: Manos Pitsidianakis
> ---
> include/exec/memattrs.h | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
Reviewed-by: Zhao Liu
-
> 2 files changed, 52 insertions(+), 1 deletion(-)
Fine for me,
Reviewed-by: Zhao Liu
++---
> rust/qemu-api/src/memory.rs | 34 --
> 3 files changed, 35 insertions(+), 21 deletions(-)
LGTM,
Reviewed-by: Zhao Liu
86/cpu.c | 37 ++-------
> target/i386/cpu.h | 12
> 2 files changed, 2 insertions(+), 47 deletions(-)
LGTM,
Reviewed-by: Zhao Liu
l allow bindgen to
> generate a bitflag using the enum variants as its domain of values.
>
> Signed-off-by: Manos Pitsidianakis
> ---
> include/exec/memattrs.h | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)>
Reviewed-by: Zhao Liu
++---
> rust/qemu-api/src/memory.rs | 34 --
> 3 files changed, 35 insertions(+), 21 deletions(-)
LGTM,
Reviewed-by: Zhao Liu
On Fri, Jul 04, 2025 at 10:45:04PM +0800, Xiaoyao Li wrote:
> Date: Fri, 4 Jul 2025 22:45:04 +0800
> From: Xiaoyao Li
> Subject: [PATCH] i386/cpu: Remove FEAT_24_0_EBX for AVX10
> X-Mailer: git-send-email 2.43.0
>
> Intel AVX10 spec has been updated to make the bit 16-18 of
Th
($derive_fn:ident, $input:expr, $($expected:tt)*) => {{
> +let input: proc_macro2::TokenStream = $input;
> +let expected: proc_macro2::TokenStream = $($expected)*;
> +let derive_fn: fn(input: syn::DeriveInput) ->
> Result =
> +$derive_fn;
> +
> +let input: syn::DeriveInput = syn::parse2(input).unwrap();
> +let result = derive_fn(input).unwrap();
> +assert_eq!(result.to_string(), expected.to_string());
> +}};
> +}
Good examples to test macros. LGTM,
Reviewed-by: Zhao Liu
> You can run the added tests directly with this meson command:
>
> meson test rust-qemu-api-macros-tests
Hi Manos, do you meet this error:
Traceback (most recent call last):
File "/usr/lib/python3/dist-packages/mesonbuild/mesonmain.py", line 146, in
run
return options.run_func(options)
---
> rust/qemu-api-macros/src/lib.rs | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Zhao Liu
b0 ("cpus: extract out kvm-specific code
> to accel/kvm") the kvm_init_cpu_signals() stub is not necessary.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> accel/stubs/kvm-stub.c | 5 -
> 1 file changed, 5 deletions(-)
Reviewed-by: Zhao Liu
;
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> accel/kvm/kvm-all.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
Reviewed-by: Zhao Liu
gt;
> Reviewed-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/qemu/accel.h | 2 +-
> accel/kvm/kvm-all.c | 4 ++--
> system/memory.c | 2 +-
> 3 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Zhao Liu
hvf-all.c | 2 +-
> accel/kvm/kvm-all.c | 2 +-
> accel/tcg/tcg-all.c | 2 +-
> 5 files changed, 5 insertions(+), 5 deletions(-)
Make sense. I think then MachineClass can also be similarly cleaned up.
Reviewed-by: Zhao Liu
gt;
> Reviewed-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/qemu/accel.h | 2 +-
> accel/kvm/kvm-all.c | 4 ++--
> system/memory.c | 2 +-
> 3 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Zhao Liu
;
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> accel/kvm/kvm-all.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
Reviewed-by: Zhao Liu
athieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> include/qemu/accel.h | 2 +-
> accel/accel-system.c | 2 +-
> accel/xen/xen-all.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Zhao Liu
;
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> accel/tcg/tcg-all.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Zhao Liu
;
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> accel/kvm/kvm-all.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Zhao Liu
>accelerator", so that we could get @accel
by ms->accelerator.
But considerring the user emulation, where the @ms is NULL, and for
these cases, it needs to bring current_accel() back in patch 32.
Anyway, this solution is also fine for me, so,
Reviewed-by: Zhao Liu
...But there'
| 1 +
> accel/accel-system.c | 3 ++-
> accel/tcg/tcg-accel-ops.c | 4 +++-
> 5 files changed, 11 insertions(+), 3 deletions(-)>
Reviewed-by: Zhao Liu
-
> include/system/accel-ops.h | 2 +-
> accel/tcg/tcg-accel-ops-icount.c | 8 +++-
> accel/tcg/tcg-accel-ops.c| 4 +---
> system/cpus.c| 12 +++-
> 6 files changed, 14 insertions(+), 16 deletions(-)
Reviewed-by: Zhao Liu
y-cpus.h| 14 ++
> include/system/cpus.h | 5 -
> accel/dummy-cpus.c| 1 +
> accel/qtest/qtest.c | 1 +
> accel/xen/xen-all.c | 1 +
> 6 files changed, 18 insertions(+), 5 deletions(-)
> create mode 100644 accel/dummy-cpus.h
Reviewed-by: Zhao Liu
-stub.c | 12
> target/i386/whpx/whpx-all.c | 7 +--
> accel/stubs/meson.build | 1 +
> 4 files changed, 28 insertions(+), 19 deletions(-)
> create mode 100644 accel/stubs/whpx-stub.c
Reviewed-by: Zhao Liu
.c | 12
> target/i386/nvmm/nvmm-all.c | 8 +---
> accel/stubs/meson.build | 1 +
> 4 files changed, 26 insertions(+), 18 deletions(-)
> create mode 100644 accel/stubs/nvmm-stub.c
With header file fixed,
Reviewed-by: Zhao Liu
;
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> include/system/accel-ops.h | 8
> include/system/hw_accel.h | 8
> 2 files changed, 16 insertions(+)
Reviewed-by: Zhao Liu
ippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> include/system/accel-ops.h | 8
> include/system/hw_accel.h | 13 +++--
> 2 files changed, 19 insertions(+), 2 deletions(-)>
Reviewed-by: Zhao Liu
: Richard Henderson
> ---
> accel/stubs/kvm-stub.c | 4
> 1 file changed, 4 deletions(-)
Reviewed-by: Zhao Liu
gt;
> No need for accel-specific @dirty field when we have
> a generic one in CPUState.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> target/i386/whpx/whpx-all.c | 23 +++
> 1 file changed, 11 insertions(+), 12 deletions(-)
Reviewed-by: Zhao Liu
gt;
> No need for accel-specific @dirty field when we have
> a generic one in CPUState.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> target/i386/nvmm/nvmm-all.c | 21 ++---
> 1 file changed, 10 insertions(+), 11 deletions(-)
Reviewed-by: Zhao Liu
hvf.c | 4 ++--
> target/i386/hvf/hvf.c | 4 ++--
> target/i386/hvf/x86hvf.c | 2 +-
> 5 files changed, 10 insertions(+), 11 deletions(-)
Reviewed-by: Zhao Liu
> accel/hvf/hvf-all.c | 268 +
> 2 files changed, 272 insertions(+), 270 deletions(-)
Reviewed-by: Zhao Liu
+
> accel/hvf/hvf-all.c | 28
> 2 files changed, 30 insertions(+), 28 deletions(-)
Reviewed-by: Zhao Liu
--
> include/system/hvf_int.h | 34 ++
> 2 files changed, 34 insertions(+), 38 deletions(-)
Reviewed-by: Zhao Liu
6 --
> accel/kvm/kvm-all.c| 6 ++
> system/cpus.c | 8 ----
> 6 files changed, 17 insertions(+), 15 deletions(-)
Reviewed-by: Zhao Liu
cel-ops.c | 1 -
> accel/kvm/kvm-all.c| 5 -
> accel/tcg/tcg-accel-ops.c | 6 --
> accel/tcg/tcg-all.c| 6 ++
> gdbstub/system.c | 8 +---
> target/arm/hvf/hvf.c | 2 +-
> target/i386/hvf/hvf.c | 2 +-
> 12 files changed, 20 insertions(+), 17 deletions(-)
Reviewed-by: Zhao Liu
ippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> accel/tcg/internal-common.h | 2 ++
> accel/tcg/monitor.c | 11 ---
> 2 files changed, 10 insertions(+), 3 deletions(-)
Reviewed-by: Zhao Liu
ippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> accel/tcg/monitor.c | 27 +--
> 1 file changed, 17 insertions(+), 10 deletions(-)
Reviewed-by: Zhao Liu
commit 1b65b4f54c7.
>
> Fixes: 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER")
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> accel/tcg/monitor.c | 6 --
> 1 file changed, 6 deletions(-)
Reviewed-by: Zhao Liu
Daudé
> Acked-by: Dr. David Alan Gilbert
> Reviewed-by: Richard Henderson
> ---
> qapi/machine.json | 18 --
> accel/tcg/monitor.c| 21 -
> tests/qtest/qmp-cmd-test.c | 1 -
> hmp-commands-info.hx | 14 --
> 4 files changed, 54 deletions(-)
Reviewed-by: Zhao Liu
e_vcpu() is only used within the same file unit.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> ---
> include/system/kvm.h | 8
> accel/kvm/kvm-all.c | 8 +++-
> 2 files changed, 7 insertions(+), 9 deletions(-)
Reviewed-by: Zhao Liu
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