I noticed the recent SH4 patches are included in the 9.0.0-rc3 release.
Is it appropriate that I request a wiki.qemu.org account so that I may document
these changes in https://wiki.qemu.org/ChangeLog/9.0 in a manner that is
consistent with how the changes to other CPUs have been documented so
in the SH-4 ISA manual.
Signed-off-by: Zack Buhman
---
target/sh4/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 6643c14dde..ebb6c901bf 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -523,6 +523,7
macl = 0x7fff
qemu saturation mac.w result (before this commit):
mach = 0x0001
macl = 0x8000
All of the above also matches the description of MAC.W as documented
in cd00147165-sh-4-32-bit-cpu-core-architecture-stmicroelectronics.pdf
Signed-off-by: Zack Buhman
---
t
Peter Maydell writes:
> On Fri, 5 Apr 2024 at 08:55, Zack Buhman wrote:
>>
>> The saturation arithmetic logic in helper_macw is not correct.
>>
>> I tested and verified this behavior on a SH7091, the general pattern
>> is a code sequence such as:
>>
&g
macl = 0x7fff
qemu saturation mac.w result (before this commit):
mach = 0x0001
macl = 0x8000
All of the above also matches the description of MAC.W as documented
in cd00147165-sh-4-32-bit-cpu-core-architecture-stmicroelectronics.pdf
Signed-off-by: Zack Buhman
---
t
Signed-off-by: Zack Buhman
- Original message -
From: "Philippe Mathieu-Daudé"
To: Peter Maydell , Zack Buhman
Cc: qemu-devel@nongnu.org, Yoshinori Sato
Subject: Re: [PATCH v2] sh4: mac.l: implement saturation arithmetic logic
Date: Friday, April 05, 2024 1:26 AM
Hi Zack,
The saturation arithmetic logic in helper_macl is not correct.
I tested and verified this behavior on a SH7091, the general pattern
is a code sequence such as:
sets
mov.l _mach,r2
lds r2,mach
mov.l _macl,r2
lds r2,macl
mova _n,r0
mov r0,r1
The saturation arithmetic logic in helper_macl is not correct.
I tested and verified this behavior on a SH7091, the general pattern
is a code sequence such as:
sets
mov.l _mach,r2
lds r2,mach
mov.l _macl,r2
lds r2,macl
mova _n,r0
mov r0,r1
commit):
first macw : macl = 0x5678 * 0xdefg + 0x0
mach = 0x0
second macw: (unaligned longword memory access, SIGBUS)
Various SH-4 ISA manuals also confirm that `mac.w` is a 16-bit word memory
access, not a 32-bit longword memory access.
Signed-off-by: Zack Buhman
---
target/sh4