> -原始邮件-
> 发件人: "Jonathan Cameron"
> 发送时间:2025-03-13 02:10:35 (星期四)
> 收件人: "Yuquan Wang"
> 抄送: qemu-devel@nongnu.org, linux-...@vger.kernel.org
> 主题: Re: [PATCH] docs/cxl: Add serial number for persistent-memdev
>
> On Wed, 5
>
> On Tue, 4 Mar 2025 14:22:48 +0800
> Yuquan Wang wrote:
>
> > >
> > > On Thu, Feb 20, 2025 at 04:12:13PM +, Jonathan Cameron wrote:
> > > > On Mon, 17 Feb 2025 19:20:39 +0800
> > > > Yuquan Wang wrote:
> > > >
&g
Add serial number parameter in the cxl persistent examples.
Signed-off-by: Yuquan Wang
---
docs/system/devices/cxl.rst | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index 882b036f5e..e307caf3f8
>
> On Thu, Feb 20, 2025 at 04:12:13PM +, Jonathan Cameron wrote:
> > On Mon, 17 Feb 2025 19:20:39 +0800
> > Yuquan Wang wrote:
> >
> > > Add serial number parameter in the cxl persistent examples.
> > >
> > > Signed-off-by: Yuquan Wa
>
> Looks good. I've queued it up on my gitlab staging tree, but
> Michael if you want to pick this one directly that's fine as well.
>
> I should be pushing out my gitlab tree shortly (bit of networking
> fun to deal with).
>
Hi, Jonathan
About qemu side, I have another question: Could the qe
Add serial number parameter in the cxl persistent examples.
Signed-off-by: Yuquan Wang
---
docs/system/devices/cxl.rst | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index 882b036f5e..e307caf3f8
On Tue, Feb 11, 2025 at 09:26:55AM +, Jonathan Cameron wrote:
> On Tue, 11 Feb 2025 10:24:13 +0800
> Yuquan Wang wrote:
>
> > The previous default value of sn is UI64_NULL which would cause the
> > cookie of nd_interleave_set be '0' and the "invalid in
the failure of label validation,
so this defines '1' as the default value of serial number to fix the
problem.
Yuquan Wang (1):
mem/cxl-type3: Add a default value of sn
hw/mem/cxl_type3.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
--
2.34.1
the failure of label validation,
so this defines '1' as the default value of serial number to fix the
problem.
Signed-off-by: Yuquan Wang
---
hw/mem/cxl_type3.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.
#x27;target_chb' to
record the target list of CXLHostBridge. And necessary is to adjust
the logic of 'cxl_cfmws_find_device' and 'cxl_fmws_link_targets' to
allow different types of cxl host bridge.
Move 'cxl_get_hb_cstate' & 'cxl_get_hb_passthrough' fr
ypes of cxl host bridge.
Move 'cxl_get_hb_cstate' & 'cxl_get_hb_passthrough' from pxb code
into cxl-host code.
Link:
[1]:
https://lore.kernel.org/linux-cxl/20220616141950.23374-1-jonathan.came...@huawei.com/
[2]: https://lists.nongnu.org/archive/html/qemu-arm/2024-11/msg00522.
o do it.
This series patches are here to hopefully some comments to guide me!
Link:
[1]: https://lists.nongnu.org/archive/html/qemu-arm/2024-12/msg00350.html
[2]:
https://lore.kernel.org/linux-cxl/20220616141950.23374-1-jonathan.came...@huawei.com/
[3]: https://edk2.groups.io/g/devel/message/120
CXL_MMIO_HIGH
To provide CFMWs on sbsa-ref, this extends 1TB space from the
hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window:
- 1T CXL_FIXED_WINDOW
Signed-off-by: Yuquan Wang
---
docs/system/arm/sbsa.rst | 4 ++
hw/arm/sbsa-ref.c| 135
#x27;target_chb' to
record the target list of CXLHostBridge. And necessary is to adjust
the logic of 'cxl_cfmws_find_device' and 'cxl_fmws_link_targets' to
allow different types of cxl host bridge.
Move 'cxl_get_hb_cstate' & 'cxl_get_hb_passthrough' fr
ypes of cxl host bridge.
Move 'cxl_get_hb_cstate' & 'cxl_get_hb_passthrough' from pxb code
into cxl-host code.
Link:
[1]:
https://lore.kernel.org/linux-cxl/20220616141950.23374-1-jonathan.came...@huawei.com/
[2]: https://lists.nongnu.org/archive/html/qemu-arm/2024-11/msg00522.
CXL_MMIO_HIGH
To provide CFMWs on sbsa-ref, this extends 1TB space from the
hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window:
- 1T CXL_FIXED_WINDOW
Signed-off-by: Yuquan Wang
---
docs/system/arm/sbsa.rst | 4 +
hw/arm/sbsa-ref.c | 139 ++-
hw
ink:
[1]:
https://lore.kernel.org/linux-cxl/20220616141950.23374-1-jonathan.came...@huawei.com/
[2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423#
[3]: https://edk2.groups.io/g/devel/topic/rfc_patch_edk2_platforms_v3/109768222
Yuquan Wang (1):
hw/arm/sbsa-ref: Support CX
awei.com/
[2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423#
[3]: https://edk2.groups.io/g/devel/topic/rfc_patch_edk2_platforms_v2/109403456
Yuquan Wang (1):
hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW
docs/system/arm/sbsa.rst | 4 ++
hw/arm/sbsa-ref.c | 122 +
To provide CFMWs on sbsa-ref, this extends 1TB space from the
hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window.
Signed-off-by: Yuquan Wang
---
docs/system/arm/sbsa.rst | 4 ++
hw/arm/sbsa-ref.c | 122 +-
hw/cxl/cxl-host-stubs.c | 2 +
hw
This adds #defines and struct typedefs for the various structure
types in the CXL3.1 CXL Early Discovery Table (CEDT).
Signed-off-by: Yuquan Wang
---
.../IndustryStandard/CxlEarlyDiscoveryTable.h | 113 ++
1 file changed, 113 insertions(+)
create mode 100644 MdePkg/Include
t cxl on Qemu sbsa-ref platform, but it relies on CXL ACPI
elements
within compiled UEFI flash instead of virt/i386 using qemu-build-Acpi tables.
Thus I
create the header file CxlEarlyDiscoveryTable.h as the fundamental format for
CEDT building
in edk2-platforms.
Yuquan Wang (1):
hanks
Yuquan Wang
>On 30.08.2024 06:15, Yuquan Wang wrote:
>> The memory layout places 1M space for 16 host bridge register regions
>> in the sbsa-ref memmap. In addition, this creates a default pxb-cxl
>> (bus_nr=0xfe) bridge with one cxl-rp on sbsa-ref.
>
>
The memory layout places 1M space for 16 host bridge register regions
in the sbsa-ref memmap. In addition, this creates a default pxb-cxl
(bus_nr=0xfe) bridge with one cxl-rp on sbsa-ref.
Signed-off-by: Yuquan Wang
---
hw/arm/sbsa-ref.c | 54 ---
1
e me!
Link:
[1]:
https://lore.kernel.org/linux-cxl/20220616141950.23374-1-jonathan.came...@huawei.com/
[2]: https://edk2.groups.io/g/devel/topic/rfc_patch_0_1/108173029
[3]: https://edk2.groups.io/g/devel/topic/rfc_patch_edk2_platforms/108173682
Yuquan Wang (2):
hw/arm/sbsa-ref: Enable CXL Ho
id=cxl-mem1 \
-hda ubuntu.ext4 \
-pflash SBSA_FLASH0.fd \
-pflash SBSA_FLASH1.fd \
I'm not sure if the new space layout would bring a series of bad
influence, this patch is here to hopefully some comments to guide me!
Signed-off-by: Yuquan Wang
---
hw/arm/sbsa-ref.c | 73 +
groups.io/g/devel/topic/rfc_patch_0_1/108173029
Yuquan Wang (2):
SbsaQemu: Add acpi0016 & acpi0017 objects into DSDT
SbsaQemu: AcpiTables: Add CEDT Table
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 30 +-
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 20 +-
Silicon/Qemu/Sb
f the new space layout would bring a series of bad
influence, but it seems that the base address and size of cxl host
bridge is ok.
Signed-off-by: Yuquan Wang
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 30 +-
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 14 +
Silicon/Qemu/SbsaQemu/A
-off-by: Yuquan Wang
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 6 +-
Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc| 70 +++
Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 7 ++
3 files changed, 82 insertions(+), 1 deletion(-)
create mode 100644 Silicon/Qemu/Sbsa
This adds #defines and struct typedefs for the various structure
types in the ACPI 6.4 CXL Early Discovery Table (CEDT).
Signed-off-by: Yuquan Wang
---
MdePkg/Include/IndustryStandard/Acpi64.h | 5 ++
.../IndustryStandard/CXLEarlyDiscoveryTable.h | 69 +++
2 files changed
build-Acpi tables.
Thus I
create the header file CXLEarlyDiscoveryTable.h as the fundamental format for
CEDT building
in edk2-platforms.
Yuquan Wang (1):
MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT
MdePkg/Include/IndustryStandard/Acpi64.h | 5 ++
.../IndustrySta
On Fri, May 10, 2024 at 06:16:46PM +0100, Jonathan Cameron wrote:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/jic23/cxl-staging.git/log/?h=arm-numa-fixes
>
Thank you :)
> I've run out of time to sort out cover letters and things + just before the
> merge
> window is never a good time get
On Wed, May 08, 2024 at 01:02:52PM +0100, Jonathan Cameron wrote:
>
> > [0.00] ACPI: SRAT: Node 0 PXM 0 [mem 0x4000-0xbfff]
> > [0.00] ACPI: SRAT: Node 1 PXM 1 [mem 0xc000-0x13fff]
> > [0.00] ACPI: Unknown target node for memory at 0x100,
> > assumi
Hello, Jonathan
Recently I run some cxl tests on qemu virt(branch:cxl-2024-04-22-draft) but met
some
problems.
Problems:
1) the virt machine could not set the right numa topology from user input;
My Qemu numa set:
-object memory-backend-ram,size=2G,id=mem0 \
-numa node,nodeid=0,cpus=0-1,memdev
This patch fixes the unit typo of interleave-granularity of
CXL Fixed Memory Window in qemu-option.hx.
Yuquan Wang (1):
qemu-options.hx: Fix typo for interleave-granularity of CFMW
qemu-options.hx | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--
2.34.1
This patch fixes the unit typo of interleave-granularity of
CXL Fixed Memory Window in qemu-option.hx.
Signed-off-by: Yuquan Wang wangyuquan1...@phytium.com.cn
---
qemu-options.hx | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index
On Mon, May 22, 2023 at 05:11:39PM -0700, Dan Williams wrote:
> Yasunori Gotou (Fujitsu) wrote:
[...]
Hi, all
There was some confusions about CXL device hotplug when I recently
tried to use Qemu to emulate CXL device hotplug and verify the relevant
functions of kernel.
> > Q1) Can PCIe hotplug d
The dev_dbg info for Clear Event Records mailbox command would report
the handle of the next record to clear not the current one.
This was because the index 'i' had incremented before printing the
current handle value.
Signed-off-by: Yuquan Wang
---
drivers/cxl/core/mbox.c | 2
hen the kernel printed:
[ 1639.106181] cxl_pci :0d:00.0: Event log '0': Clearing 0
However, the line 36 in 'hw/cxl/cxl-events.c': log->next_handle = 1;
It will set the actual handle value of injected event to '1'.
With this fix, the kernel will print:
[ 122
to 'clear_cnt'
which can be easier for developers to distinguish and understand.
Signed-off-by: Yuquan Wang
---
drivers/cxl/core/mbox.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 9ad
hen the kernel printed:
[ 1639.106181] cxl_pci :0d:00.0: Event log '0': Clearing 0
However, the line 36 in 'hw/cxl/cxl-events.c': log->next_handle = 1;
It will set the actual handle value of injected event to '1'.
With this fix, the kernel will print:
[ 122.
Hello, Jonathan
When during the test of qmps of CXL events like
"cxl-inject-general-media-event",
I am confuesd about the argument "flags". According to "qapi/cxl.json" in qemu,
this argument represents "Event Record Flags" in Common Event Record Format.
However, it seems like the specific 'Eve
On 2024-03-07 20:10, jonathan.cameron wrote:
> Hack is fine the relevant device with lspci -tv and then use
> setpci -s 0d:00.0 0x208.l=0
> to clear all the mask bits for uncorrectable errors.
Thanks! The suggestions from you and Terry did work!
BTW, is my understanding below about CXL RAS corr
Hello, Jonathan
Recently I met some problems on CXL RAS tests.
I tried to use "cxl-inject-uncorrectable-errors" and
"cxl-inject-correctable-error"
qmp to inject CXL errors, however, there was no any kernel printing information
in
my qemu machine. And the qmp connection was unstable that made
Hi, Jonathan
On 2023-09-05 22:34, jonathan.cameron wrote:
>
> As I understand it the distinction is more about the format / contents of
> that memory
> than how you access them.
Yes, RCH DP RCRB includes registers from PCIe Type 1 Config Header and
PCIe capabilities and extended capabilities w
Hi, Jonathan
On 2023-09-04 20:43, jonathan.cameron wrote:
>
> At the system design level, MMIO space of Root complex register space via RCRB
> does not map in a similar fashion to PCIE MMIO space (which is handled via
> address decoding in the PCIE fabric). It is much more similar to MMIO for
>
This extends the slots of xhci to 64, since the default xhci_sysbus
just supports one slot.
Signed-off-by: Wang Yuquan
Signed-off-by: Chen Baozi
---
hw/arm/sbsa-ref.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 64e1cbce17..bc89eb4806 100644
--
As the default xhci_sysbus just supports only one usb slot, it can not
meet the working requirement of this bord. Therefore, we extend the
slots of xhci to 64.
Yuquan Wang (1):
hw/arm/sbsa-ref: set 'slots' property of xhci
hw/arm/sbsa-ref.c | 1 +
1 file changed, 1 insertion(+)
--
2.34.1
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.
Bumping platform version to 0.3 with this change.
Signed-off-by: Y
Please review the change.
- sbsa-ref: Replace EHCI with XHCI on sysbus.
This work bumps the platform version directly to 0.3 because
the addition of ITS will take sbsa-ref to 0.2 version.
Yuquan Wang (1):
hw/arm/sbsa-ref: use XHCI to replace EHCI
docs/system/arm/sbsa.rst | 2 +-
hw/arm
On 2023-06-21 01:24, Leif wrote:
> Leif, do you think we should bump the minor version here?
I think that makes sense, yes.
/
Leif
Thanks for everyone's guidance.
There is a new confusion: Which minor version should I bump to (2 or 3) ?
As I found that Marcin’s latest patch (add ITS sup
Hi, Gregory
There is one confusion about CXL in QEMU I hope to consult.
If you have some time to look at this email, I would have better understanding
of CXL
emulation in QEMU.
On docs/system/devices/cxl.rst , Gregory wrote:
A very simple setup with just one directly attached CXL Type 3 Volat
Please review the change.
- sbsa-ref: Replace EHCI with XHCI on sysbus.
This version updates relevant Kconfig and sbsa.rst file.
Yuquan Wang (1):
hw/arm/sbsa-ref: use XHCI to replace EHCI
docs/system/arm/sbsa.rst | 2 +-
hw/arm/Kconfig | 2 +-
hw/arm/sbsa-ref.c| 21
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses system bus XHCI to provide a usb controller with
64-bit DMA capablity instead of EHCI.
Signed-off-by: Yuquan Wang
---
docs/system/arm/sbsa.rst
Hi, Marcin
On Mon, 5 Jun 2023 11:59:16 +0200, Marcin Juszkiewicz wrote:
>
> W dniu 5.06.2023 o 11:55, Yuquan Wang pisze:
> > The current sbsa-ref cannot use EHCI controller which is only
> > able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
> > Hence
Please review the change.
- sbsa-ref: Replace EHCI with XHCI on sysbus.
Yuquan Wang (1):
hw/arm/sbsa-ref: use XHCI to replace EHCI
hw/arm/sbsa-ref.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
--
2.34.1
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.
Signed-off-by: Yuquan Wang
---
hw/arm/sbsa-ref.c
Hi, Leif
On Thu, 1 Jun 2023 18:59:56 +0100, Leif Lindholm wrote:
>
> +Ard
>
> On Thu, Jun 01, 2023 at 16:01:43 +0100, Peter Maydell wrote:
> > > >> Also has EHCI never worked, or has it worked in some modes and so this
> > > >> change should be versioned?
> > > >
> > > > AIUI, EHCI has never wor
Please review the change.
- sbsa-ref: Add an XHCI on PCIe bus to provide an availiable
usb controller.
Yuquan Wang (1):
hw/arm/sbsa-ref: add XHCI controller on PCIe
hw/arm/sbsa-ref.c | 2 ++
1 file changed, 2 insertions(+)
--
2.34.1
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this add an XHCI on PCIe to provide a usb controller with 64-bit
DMA capablity.
Signed-off-by: Yuquan Wang
---
hw/arm/sbsa-ref.c | 2 ++
1 file chang
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.
Signed-off-by: Yuquan Wang
Chan
Please review the change.
- Replace EHCI with XHCI on sbsa-ref board.
v1 patchset has fixed my commit rebase problem in the last version.
Yuquan Wang (1):
hw/arm/sbsa-ref: use XHCI to replace EHCI
hw/arm/sbsa-ref.c | 16
1 file changed, 8 insertions(+), 8 deletions
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