[PATCH 2/2] hw/riscv: virt: fix pmu subnode paths

s/simple-bus.yaml This patch moves the pmu to top level to make the dt-validate happy. Signed-off-by: Yu Chien Peter Lin --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4e3efbee16..be8f0cb26e 100644 --- a/hw/riscv/virt.

[PATCH 1/2] target: riscv: fix typos

Fix a few minor typos for PMU events. Signed-off-by: Yu Chien Peter Lin --- target/riscv/cpu.h| 2 +- target/riscv/cpu_helper.c | 2 +- target/riscv/pmu.c| 8 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

Re: [PATCH] target/riscv: Fix PMU node property for virt machine

Hi Conor, Thank you for your prompt response. On Fri, Apr 21, 2023 at 06:59:40PM +0100, Conor Dooley wrote: > On Fri, Apr 21, 2023 at 09:14:37PM +0800, Yu Chien Peter Lin wrote: > > The length of fdt_event_ctr_map[20] will add 5 dummy cells in > > "riscv,event-to-mhpmco

[PATCH] target/riscv: Fix PMU node property for virt machine

0x10021 to RISCV_PMU_EVENT_CACHE_ITLB_READ_MISS. Signed-off-by: Yu Chien Peter Lin --- $ ./build/qemu-system-riscv64 -M virt,dumpdtb=/tmp/virt.dtb -cpu rv64,sscofpmf=on && dtc /tmp/virt.dtb | grep mhpmcounters [...] riscv,event-to-mhpmcounters = <0x01 0x01 0x7fff9