On 2025/7/16 12:05, Konstantin Belousov wrote:
On Wed, Jul 16, 2025 at 12:01:44PM +0800, Yi Liu wrote:
On 2025/7/15 20:27, CLEMENT MATHIEU--DRIF wrote:
On 15/07/2025 10:27 am, David Woodhouse wrote:
On Tue, 2025-07-15 at 06:11 +, CLEMENT MATHIEU--DRIF wrote:
On 14/07/2025 11:22 pm
2025 15:28:09 GMT+01:00, Yi Liu
wrote:
Hi David,
On 2025/7/14 16:00, David Woodhouse wrote:
From: David Woodhouse
I think this "if branch" can be moved just after the inv_desc non-zero
reserved bit checking. Hence you don't need a ret at all. :)
We want to return false if t
Woodhouse wrote:
On 14 July 2025 15:28:09 GMT+01:00, Yi Liu wrote:
Hi David,
On 2025/7/14 16:00, David Woodhouse wrote:
From: David Woodhouse
FreeBSD does both, and this appears to be perfectly valid. The VT-d
spec even talks about the ordering (the status write should be done
first
inv_desc->lo);
return false;
}
I think this "if branch" can be moved just after the inv_desc non-zero
reserved bit checking. Hence you don't need a ret at all. :) btw. I'm
also asking if VT-d spec allows it or not. So let's wait for a while..
-return true;
+return ret;
}
static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
--
Regards,
Yi Liu
On 2025/6/17 21:11, Jason Gunthorpe wrote:
On Tue, Jun 17, 2025 at 09:03:32PM +0800, Yi Liu wrote:
I suggest fixing the Linux driver to refuse to run in sm_on mode if
the HW supports scalable mode and ecap_slts = false. That may not be
100% spec compliant but it seems like a reasonable approach
AMD has the same issues, BTW, arguably even worse as I didn't notice
any way to specify if the v1 page table is supported :\
Jason
--
Regards,
Yi Liu
with the PASID cache.
To aovid confusion, maybe better to say cached pasid entry. :)
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 26
include/hw/i386/intel_iommu.h | 6 +
hw/i386/intel_iommu.c | 252
ache_gen) {
*ce = cc_entry->context_entry;
+vtd_iommu_unlock(s);
return 0;
} else {
+vtd_iommu_unlock(s);
return vtd_dev_to_context_entry(s, bus_num, devfn, ce);
}
}
Which one do you prefer?
If it's just optimization, perhaps just drop it. :)
--
Regards,
Yi Liu
en reading the first line, it makes me thinking why need the helpers
since there is already a helper to find. The key is the later part. We need
to translate the PCI_NO_PASID to ridpasid.
OK, presume you want me to delete first line.
Let me know if you mean not.
yes. :)
Regards,
Yi Liu
ith normal requirement. :)
I can think of ERRATA_772415 and NESTED capability. NESTED used for creating
VFIO default HWPT in stage2 mode.
yeah. NESTED should be a hard requirement. VFIO should allocate hwpt with
nested_parent flag.
--
Regards,
Yi Liu
On 2025/6/17 11:22, Nicolin Chen wrote:
On Mon, Jun 16, 2025 at 03:38:26PM +0800, Yi Liu wrote:
On 2025/6/16 13:59, Nicolin Chen wrote:
On Thu, Jun 12, 2025 at 08:53:40PM +0800, Yi Liu wrote:
That being said, IOMMU_NOTIFIER_IOTLB_EVENTS should not be needed
for passthrough devices, right
cause
I don't want to bring complexity to VFIO just for an Errata. I remember
ERRATA_772415 exists only on old SPR, @Liu, Yi L can correct me if I'm wrong.
hmmm. I'm fine to pass some info to vfio hence let vfio skip RO mappings.
Is there other info that VFIO needs to get from vIOMMU? Hope start adding
such mechanism with normal requirement. :)
--
Regards,
Yi Liu
On 2025/6/16 13:59, Nicolin Chen wrote:
On Thu, Jun 12, 2025 at 08:53:40PM +0800, Yi Liu wrote:
That being said, IOMMU_NOTIFIER_IOTLB_EVENTS should not be needed
for passthrough devices, right?
No, even if x-flts=on is configured in QEMU cmdline, that only mean virtual vtd
supports stage-1
can further simplify the routine
by allocating a nesting parent HWPT in iommufd_cdev_attach(),
as long as the attaching device is identified as "passthrough"
and there is "iommufd" in its "-device" string?
After all, IOMMU_HWPT_ALLOC_NEST_PARENT is a common f
w_page_hook(const IOMMUTLBEvent *event,
void *private)
{
--
Regards,
Yi Liu
-if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) {
+ if (vtd_as_to_context_entry(vtd_as, &ce) == 0) {
trace_vtd_replay_ce_valid(s->root_scalable ? "scalable mode" :
"legacy mode",
bus_n, PCI_SLOT(vtd_as->devfn),
--
Regards,
Yi Liu
: Zhenzhong Duan
Reviewed-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Yi Liu
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 69d72ad35c..f0b1f90eff 100644
--- a/hw/i386/intel_iommu.c
E_VFIO_PCI_BASE,
-.instance_size = sizeof(VFIOPCIDevice),
.class_init = vfio_pci_dev_class_init,
.instance_init = vfio_instance_init,
.instance_finalize = vfio_instance_finalize,
LGTM.
Reviewed-by: Yi Liu
--
Regards,
Yi Liu
:15PM +0800, Yi Liu wrote:
Hey Nic,
On 2025/5/22 06:49, Nicolin Chen wrote:
On Wed, May 21, 2025 at 07:14:45PM +0800, Zhenzhong Duan wrote:
+static const MemoryListener iommufd_s2domain_memory_listener = {
+.name = "iommufd_s2domain",
+.priority = 1000,
+.
d allocate an S1
HWPT for device to attach. Starting from here, get_address_space()
can return the iommu address space -- on ARM, we only need it for
KVM to translate MSI.
refer to the last reply. This seems to be different between ARM and VT-d
emulation.
--
Regards,
Yi Liu
ways there
for use.
does vtd_host_dma_iommu() have to return the iommu address space
all the time?
yes, all the time.
--
Regards,
Yi Liu
n unrelated cleanup.
Yeah unrelated cleanup. Although I don't understand why these
code paths don't use memory_region_transaction_begin/commit and
have to access BQL.
The below two functions would call memory_region_transaction_begin/commit().
So these paths need BQL.
memory_region
---
hw/i386/intel_iommu.c | 10 ++
1 file changed, 10 insertions(+)
Reviewed-by: Yi Liu
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index dffd7ee885..fea2220013 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -4216,6 +4216,7 @@ VTDAddressSpace
aro.org
Signed-off-by: Peter Maydell
Is this workflow making sense and accepted? Otherwise what should
we change? Maybe clarify along with the tags; or including all
Message-Id could make this easier to track?
Commit eda4c9b5b3c is the similar case. Zhenzhong and Clément took
the patch fro
well. But
it checks PCI_NO_PASID against the pasid instead of vtd_pas->pasid.
So it looks confusing to me.
--
Regards,
Yi Liu
Reviewed-by: Yi Liu
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 75ccd501b0..4323fc5d6d 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -410,6 +410,9 @@ typedef union VTDInvDesc VTDInvDesc;
will result in invalidation queue error."
Current code missed to send IQE event to guest, fix it.
a nit: mention the spec revision as well since the Figure number may be
modified.
Reviewed-by: Yi Liu
Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support")
Suggested-by
ainly used to help debug guest error, but it only dumps once in
qemu life cycle and doesn't help much, we need error_report() instead.
Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support")
Suggested-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_int
er). :)
Got it, just double confirm you prefer x-flts, not x-fsts?
x-flts as most of the code use flt instead of fst.
--
Regards,
Yi Liu
better as it suits more how spec tells it (FSTS in the eap
register). :)
--
Regards,
Yi Liu
different call sites. This isn't an issue as error_report_once()
here is mainly used to help debug guest error, but it only dumps once in
qemu life cycle and doesn't help much, we need error_report() instead.
Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support")
Suggeste
On 2024/11/4 15:37, CLEMENT MATHIEU--DRIF wrote:
On 04/11/2024 03:49, Yi Liu wrote:
Caution: External email. Do not open attachments or click links, unless
this email comes from a known sender and you know the content is safe.
On 2024/9/30 17:26, Zhenzhong Duan wrote:
Per spec 6.5.2.4
-
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 27 +--
2 files changed, 22 insertions(+), 6 deletions(-)
anyhow, this patch looks good to me.
Reviewed-by: Yi Liu
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
i
-Drif
---
include/hw/i386/intel_iommu.h | 2 +-
hw/i386/intel_iommu.c | 10 +-
2 files changed, 10 insertions(+), 2 deletions(-)
Reviewed-by: Yi Liu
--
Regards,
Yi Liu
rn mode is supported. When enabled in legacy mode, throw out error.
With scalable modern mode exposed to user, also accurate the pasid entry
check in vtd_pe_type_check().
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
Maybe a Suggested-by tag can help to understand where
during walking Intel
VT-d stage-1 page table.
This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
Reviewed-by: Clément Mathieu--Drif
Acked-by: Jason Wang
---
hw/i386
On 2024/11/4 11:05, Duan, Zhenzhong wrote:
-Original Message-
From: Liu, Yi L
Sent: Sunday, November 3, 2024 10:22 PM
Subject: Re: [PATCH v4 06/17] intel_iommu: Implement stage-1 translation
On 2024/9/30 17:26, Zhenzhong Duan wrote:
From: Yi Liu
This adds stage-1 page table
rning
Reviewed-by: Yi Liu
This property has no effect when vIOMMU isn't in scalable modern
mode.
Signed-off-by: Zhenzhong Duan
Reviewed-by: Clément Mathieu--Drif
---
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 5 -
2 files changed, 5 insertions(+), 1 deletio
n scalable mode, first stage translation also known as scalable
modern mode is supported. When enabled in legacy mode, throw out error.
With scalable modern mode exposed to user, also accurate the pasid entry
check in vtd_pe_type_check().
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Sig
PRI is also a missing part. :)
--
Regards,
Yi Liu
ST_AW_39BIT &&
s->aw_bits != VTD_HOST_AW_48BIT) {
error_setg(errp, "%s mode: supported values for aw-bits are: %d, %d",
--
Regards,
Yi Liu
event.entry.addr_mask = size - 1;
+event.entry.translated_addr = 0;
+memory_region_notify_iommu(&vtd_as->iommu, 0, event);
+}
+ }
}
static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
--
Regards,
Yi Liu
rn sid == target_sid;
+
+return (as_key->pasid == target.pasid) &&
+ (sid == target.sid);
hence using target->pasid and target->sid here. Otherwise, looks good to me.
Reviewed-by: Yi Liu
}
-static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, u
break;
+case VTD_INV_DESC_DEV_PIOTLB:
+trace_vtd_inv_desc("device-piotlb", inv_desc.hi, inv_desc.lo);
+if (!vtd_process_device_piotlb_desc(s, &inv_desc)) {
+return false;
+}
+break;
+
case VTD_INV_DESC_DEVICE:
trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo);
if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
--
Regards,
Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote:
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong
Duan
Reviewed-by: Clément Mathieu--Drif
Acked-by: Jason Wang
---
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 27 +--
2 files changed, 22 insertions(+), 6 deletions(-)
anyhow, this patch looks good to me.
Reviewed-by: Yi Liu
diff --
+}
+break;
+
case VTD_INV_DESC_WAIT:
trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo);
if (!vtd_process_wait_desc(s, &inv_desc)) {
@@ -2793,7 +2880,6 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
* iommu driver) work, just return true is enough so far.
*/
case VTD_INV_DESC_PC:
-case VTD_INV_DESC_PIOTLB:
if (s->scalable_mode) {
break;
}
--
Regards,
Yi Liu
deletion(-)
Reviewed-by: Yi Liu
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 57c50648ce..4c3e75e593 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -324,6 +324,7 @@ typedef enum VTDFaultReason {
/* Output address in
On 2024/9/30 17:26, Zhenzhong Duan wrote:
From: Yi Liu
This adds stage-1 page table walking to support stage-1 only
translation in scalable modern mode.
Signed-off-by: Yi Liu
Co-developed-by: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Yi Sun
Signed-off-by
/i386/intel_iommu.c | 23 +++
2 files changed, 25 insertions(+)
Reviewed-by: Yi Liu
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 38bf0c7a06..57c50648ce 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386
evice passthrough until nesting
is supported.
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
Acked-by: Jason Wang
---
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 23 ++-
2 files changed, 19 insertions(+), 5 deletions(-)
Reviewed-by: Yi Liu
ow user to control the setting.
Use hw_compat_9_1 to handle the compatibility for machines before 9.2 which
is hw_compat_9_1 a typo? Looks to be pc_compat_9_1. :)
Otherwise I think it is good.
Reviewed-by: Yi Liu
allow guest to set the field. Starting from 9.2, this field is reserved(0)
by
On 2024/9/11 13:22, Zhenzhong Duan wrote:
From: Yi Liu
This adds stage-1 page table walking to support stage-1 only
transltion in scalable modern mode.
a typo. s/tansltion/translation/
Signed-off-by: Yi Liu
Co-developed-by: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
On 2024/9/11 13:22, Zhenzhong Duan wrote:
From: Yi Liu
Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation,
rename variable and functions from slpte to pte whenever possible.
But some are SST only, they are renamed with sl_ prefix.
Signed-off-by: Yi Liu
Co-developed
e the translation request."
sorry for a typo. s/request/result/
--
Regards,
Yi Liu
's suggestion,
only vIOMMU properties can control them.
I see. yeah, it makes sense.
--
Regards,
Yi Liu
gt;iommu, 0, event);
+}
+ }
}
static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
--
Regards,
Yi Liu
vIOMMU when comes to support passthrough devices.
Yes, we already have this check, see
https://github.com/yiliu1765/qemu/commit/b7ac7ce3a2e21eb1b3172743ee6f73e80fe67b3a
good to know it. :) Will you fail the VM if the device's iommu does not
support FS1GP or just mask out the FS1GP?
--
Regards,
Yi Liu
n false;
+}
+return true;
+}
+
static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
@@ -2775,6 +2852,10 @@ static bool
vtd_process_inv_desc(IntelIOMMUState *s)
break;
case VTD_INV_DESC_PIOTLB:
+trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]);
+if (!vtd_process_piotlb_desc(s, &inv_desc)) {
+return false;
+}
break;
case VTD_INV_DESC_WAIT:
--
Regards,
Yi Liu
--
Regards,
Yi Liu
break;
case VTD_INV_DESC_PIOTLB:
+trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]);
+if (!vtd_process_piotlb_desc(s, &inv_desc)) {
+return false;
+}
break;
case VTD_INV_DESC_WAIT:
--
Regards,
Yi Liu
48BIT) && s->scalable_modern) {
+error_setg(errp, "Supported values for aw-bits are: %d",
+ VTD_HOST_AW_48BIT);
call out it is for scalable modern.:)
+return false;
+}
+
if (s->scalable_mode && !s->dma_drain) {
error_setg(errp, "Need to set dma_drain for scalable mode");
return false;
--
Regards,
Yi Liu
t;ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
}
--
Regards,
Yi Liu
uot;,"
+ "pasid=0x%" PRIx32 ")", __func__, iova, pasid);
+return -VTD_FR_FS_NON_CANONICAL;
+}
+
while (true) {
offset = vtd_iova_level_offset(iova, level);
flpte = vtd_get_pte(addr, offset);
--
Regards,
Yi Liu
return -VTD_FR_FS_BIT_UPDATE_FAILED;
+}
*flptep = flpte;
*flpte_level = level;
return 0;
--
Regards,
Yi Liu
make scalable mode
work")
4a4f219e8a10 would be better. :)
Suggested-by: Yi Liu
Signed-off-by: Zhenzhong Duan
Reviewed-by: Clément Mathieu--Drif
Reviewed-by: Yi Liu
---
hw/i386/intel_iommu.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git
emulation")
Suggested-by: Yi Liu
Signed-off-by: Zhenzhong Duan
Reviewed-by: Clément Mathieu--Drif
---
hw/i386/intel_iommu.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
Reviewed-by: Yi Liu
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index c52912f
, /*Invalid PASID table entry */
how about making the comment line aligned? Either one line or two lines.
Besides this, lgtm.
Reviewed-by: Yi Liu
/* Output address in the interrupt address range for scalable mode */
VTD_FR_SM_INTERRUPT_ADDR = 0x87,
diff --git a/hw/i386
safe.
In vtd_process_inv_desc(), VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB are
bypassed without scalable mode check. These two types are not valid
in legacy mode and we should report error.
Suggested-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 22 +++---
On 2024/8/13 15:44, Zhenzhong Duan wrote:
In vtd_process_inv_desc(), VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB are
bypassed without scalable mode check. These two types are not valid
in legacy mode and we should report error.
Suggested-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/i386
problem for now as bits[11:9]
is zero for all current invalidation types. But it will break if newer
type occupies bits[11:9].
Fix it by take bits[11:9] into type and make reserved bits check accurate.
s/take/taking/
Reviewed-by: Yi Liu
There is another fix you may add. In vtd_process_inv_desc(), it
794,7 @@ struct MemoryRegion {
bool unmergeable;
uint8_t dirty_log_mask;
bool is_iommu;
+bool no_dma;
RAMBlock *ram_block;
Object *owner;
/* owner as TYPE_DEVICE. Used for re-entrancy checks in MR access hotpath
*/
--
Regards,
Yi Liu
On 2024/7/29 16:42, Michael S. Tsirkin wrote:
On Mon, Jul 29, 2024 at 03:39:03PM +0800, Yi Liu wrote:
On 2024/7/18 16:16, Zhenzhong Duan wrote:
From: Yu Zhang
Spec revision 3.0 or above defines more detailed fault reasons for
scalable mode. So introduce them into emulation code, see spec
ee VT-d
spec has any definition on it. So it should just be a software trick. :)
[1]
https://lore.kernel.org/qemu-devel/1408168544-28605-3-git-send-email-tamlokv...@gmail.com/
[2] https://lore.kernel.org/qemu-devel/20190301065219.GA9@xz-x1/
--
Regards,
Yi Liu
| 11 ++
hw/vfio/iommufd.c | 170 -
hw/vfio/migration.c| 12 +-
hw/vfio/pci.c | 3 +
backends/trace-events | 3 +
11 files changed, 318 insertions(+), 23 deletions(-)
--
Regards,
Yi Liu
y checking the debugfs output, and it looks to miss
the DW bit. is it? Put a clearer commit message would be helpful.
Please address Michael's comment, add a "Fixes: xxx" tag and resend.
--
Regards,
Yi Liu
/ecap initialization,
compatibility check and block host device passthrough until nesting
is supported.
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 2 ++
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c
On 2024/7/15 16:21, Zhao Liu wrote:
For qemu_open_old(), osdep.h said:
Don't introduce new usage of this function, prefer the following
qemu_open/qemu_create that take an "Error **errp".
So replace qemu_open_old() with qemu_open().
Cc: Yi Liu
Cc: Eric Auger
Cc: Zhenzhong D
er to refine
the commit message a bit.
Reviewed-by: Yi Liu
Signed-off-by: Clément Mathieu--Drif
Reviewed-by: Minwoo Im
---
hw/i386/intel_iommu_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Yi Liu
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index cbc4030031..faea23e8d6 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -264,10 +264,10 @@
#define VTD_FRCD_FR
On 2024/7/9 10:51, Jason Wang wrote:
On Mon, Jul 8, 2024 at 3:04 PM Yi Liu wrote:
On 2024/7/5 19:01, CLEMENT MATHIEU--DRIF wrote:
From: Clément Mathieu--Drif
The constant must be unsigned, otherwise the two's complement
overrides the other fields when a PASID is present.
c VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s,
uint16_t source_id,
{
struct vtd_iotlb_key key;
VTDIOTLBEntry *entry;
-int level;
+unsigned level;
for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
key.gfn = vtd_get_iotlb_gfn(addr, level);
R
nt32_t pasid;
uint64_t addr;
-uint8_t mask;
+uint64_t mask;
};
typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo;
--
Regards,
Yi Liu
L; level < VTD_SL_PML4_LEVEL; level++) {
key.gfn = vtd_get_iotlb_gfn(addr, level);
--
Regards,
Yi Liu
nt64_t mask;
};
typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo;
--
Regards,
Yi Liu
ot;Fixes tag" is not needed.
Signed-off-by: Clément Mathieu--Drif
Reviewed-by: Yi Liu
Reviewed-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index f8cf
Signed-off-by: Yi Liu
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6725913c8b..61724b91d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3656,6 +3656,7 @@ F: tests/uefi-test-tools/
VT-d Emulation
M: Michael S. Tsirkin
R: Jason Wang
+R
On 2024/7/5 13:13, CLEMENT MATHIEU--DRIF wrote:
On 05/07/2024 05:03, Yi Liu wrote:
Caution: External email. Do not open attachments or click links,
unless this email comes from a known sender and you know the content
is safe.
On 2024/5/30 20:24, CLEMENT MATHIEU--DRIF wrote:
This series
the sentence. :)
Fixes: 1b2b12376c ("intel-iommu: PASID support")
you need more digits per the result of "grep Fixes
docs/devel/submitting-a-patch.rst".
docs/devel/submitting-a-patch.rst:add an additional line with "Fixes:
Signed-off-by: Clément Mathieu--Drif
Reviewed-by
cie_regs.h | 4 +
system/memory.c| 49 ++
10 files changed, 604 insertions(+), 2 deletions(-)
--
Regards,
Yi Liu
" (unknown type)", __func__, inv_desc->hi,
--
Regards,
Yi Liu
truct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo;
--
2.45.2
--
Regards,
Yi Liu
On 2024/7/4 12:30, CLEMENT MATHIEU--DRIF wrote:
On 03/07/2024 14:14, Yi Liu wrote:
Caution: External email. Do not open attachments or click links,
unless this email comes from a known sender and you know the content
is safe.
On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
From: Clément
On 2024/7/4 12:36, CLEMENT MATHIEU--DRIF wrote:
On 03/07/2024 14:32, Yi Liu wrote:
Caution: External email. Do not open attachments or click links,
unless this email comes from a known sender and you know the content
is safe.
Hi, thanks for your review! very efficient!
Hi CMD,
I've
ATHIEU--DRIF wrote:
From: Clement Mathieu--Drif
This series belongs to a list of series that add SVM support for VT-d.
As a starting point, we use the series called 'intel_iommu: Enable stage-1
translation' (rfc2) by Zhenzhong Duan and Yi Liu.
Here we focus on the implementation of ATS
, no_write, result,
+ result_length, err_count);
+}
+
void memory_region_notify_iommu_one(IOMMUNotifier *notifier,
IOMMUTLBEvent *event)
{
--
Regards,
Yi Liu
AP_WIDTH_SHIFT 8
#define PCI_PASID_CTRL0x06/* PASID control register */
#define PCI_PASID_CTRL_ENABLE0x0001 /* Enable bit */
#define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */
--
Regards,
Yi Liu
*flptep = flpte;
-*flpte_level = level;
return 0;
}
addr = vtd_get_pte_addr(flpte, aw_bits);
-level--;
+(*flpte_level)--;
}
}
--
Regards,
Yi Liu
On 2024/7/2 23:29, CLEMENT MATHIEU--DRIF wrote:
On 02/07/2024 15:33, Yi Liu wrote:
Caution: External email. Do not open attachments or click links,
unless this email comes from a known sender and you know the content
is safe.
On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
From: Clément
On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote:
From: Clement Mathieu--Drif
This series belongs to a list of series that add SVM support for VT-d.
As a starting point, we use the series called 'intel_iommu: Enable stage-1
translation' (rfc2) by Zhenzhong Duan and Yi Liu.
Here w
nable stage-1
translation' (rfc2) by Zhenzhong Duan and Yi Liu.
Here we focus on the implementation of ATS support in the IOMMU and on a
PCI-level
API for ATS to be used by virtual devices.
This work is based on the VT-d specification version 4.1 (March 2023).
Here is a link to a GitHub
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