[PATCH] hw/char/bcm2835_aux: Fix incorrect interrupt ID when RX disabled

/bcm2835/bcm2835-peripherals.pdf Signed-off-by: Chung-Yi Chen --- hw/char/bcm2835_aux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c index c6e7eccf7d..9b073fc330 100644 --- a/hw/char/bcm2835_aux.c +++ b/hw/char/bcm2835_aux.c @@ -98,7

[PATCH v5] target/riscv: fix H extension TVM trap

or VS-mode executes SFENCE.VMA/SINVAL.VMA with HSTATUS.VTVM enabled. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA. Signed-off-by: Yi Chen Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- Rebase the patch on https

[PATCH v4] target/riscv: fix H extension TVM trap

or VS-mode executes SFENCE.VMA/SINVAL.VMA with HSTATUS.VTVM enabled. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA. Signed-off-by: Yi Chen Reviewed-by: Weiwei Li --- Add reviewed-by Replace "env->priv

[PATCH v3] target/riscv: fix H extension TVM trap

or VS-mode executes SFENCE.VMA/SINVAL.VMA with HSTATUS.VTVM enabled. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA. Signed-off-by: Yi Chen --- target/riscv/csr.c | 56 +--- target/riscv