Re: [PATCH] arm/cpu: revises cortex-r5

On Mon, 2025-01-27 at 09:03 +0100, Philippe Mathieu-Daudé wrote: > Hi, > > On 26/1/25 12:43, Yanfeng Liu wrote: > > From: Yanfeng Liu > > > > This enables generic timer feature for Cortex-R5 so that to support guests > > like NuttX RTOS. > > QEMU aims

[PATCH] arm/cpu: revises cortex-r5

From: Yanfeng Liu This enables generic timer feature for Cortex-R5 so that to support guests like NuttX RTOS. Signed-off-by: Yanfeng Liu --- target/arm/tcg/cpu32.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index

Re: [PATCH v2] riscv/gdb: add virt mode debug interface

On Mon, 2024-12-16 at 15:33 +1000, Alistair Francis wrote: > On Thu, Dec 5, 2024 at 7:17 PM Yanfeng Liu wrote: > > > > On Thu, 2024-12-05 at 08:10 +, Alex Bennée wrote: > > > Yanfeng Liu writes: > > > > > > > On Wed, 2024-12-04 at 17:03 +0100, M

[PATCH v4] riscv/gdbstub: add V bit to priv reg

This adds virtualization mode (V bit) as bit(2) of register `priv` per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. Note that GDB may display `INVALID` tag for `priv` reg when V bit is set, this doesn't affect actual access to the bit though. Signed-off-by: Yanfen

Re: [PATCH v3] riscv/gdb: add V bit to priv register

On Fri, 2024-12-13 at 10:04 +0100, Mario Fleischmann wrote: > Hi, > > apologies for the delayed review; I've just gotten to it now. > > On 06.12.2024 01:14, Yanfeng Liu wrote: > > This adds virtualization mode (V bit) as bit(2) of register `priv` > > per RiscV deb

[PATCH v3] riscv/gdb: add V bit to priv register

This adds virtualization mode (V bit) as bit(2) of register `priv` per RiscV debug spec v1.0.0-rc3. Checked with gdb-multiarch v12.1. Note that GDB may display `INVALID` tag for the value when V bit is set, this doesn't affect accessing to the bit. Signed-off-by: Yanfeng Liu --- target/

Re: [PATCH v2] riscv/gdb: add virt mode debug interface

On Thu, 2024-12-05 at 08:10 +, Alex Bennée wrote: > Yanfeng Liu writes: > > > On Wed, 2024-12-04 at 17:03 +0100, Mario Fleischmann wrote: > > > Hi everyone, > > > > > > I'd like to chime in here because we are sitting on a similar patch > &g

Re: [PATCH v2] riscv/gdb: add virt mode debug interface

isor support, `(qemu) info registers` isn't enough. We need to > have both read and write access to the V-bit. > > On 04.12.2024 14:43, Yanfeng Liu wrote: > > On Fri, 2024-11-29 at 09:59 +, Alex Bennée wrote: > > > Yanfeng writes: > > > > > > >

Re: [PATCH v2] riscv/gdb: add virt mode debug interface

On Fri, 2024-11-29 at 09:59 +, Alex Bennée wrote: > Yanfeng writes: > > > On Thu, 2024-11-28 at 14:21 +, Alex Bennée wrote: > > > Yanfeng Liu writes: > > > > > > > This adds `virt` virtual register on debug interface so that users > >

[PATCH v2] riscv/gdb: add virt mode debug interface

This adds `virt` virtual register on debug interface so that users can access current virtualization mode for debugging purposes. Signed-off-by: Yanfeng Liu --- gdb-xml/riscv-32bit-virtual.xml | 1 + gdb-xml/riscv-64bit-virtual.xml | 1 + target/riscv/gdbstub.c | 18