[PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs

When supervisor CSRs are accessed from VU-mode, a virtual instruction exception should be raised instead of an illegal instruction. Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking) Signed-off-by: Xu Lu --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs

FYI, the discussion about whether vs insn fault or illegal insn fault should be raised can be found from [1]. [1] https://lists.riscv.org/g/tech-privileged/message/2469 On Tue, Jul 8, 2025 at 2:07 PM Xu Lu wrote: > > When supervisor CSRs are accessed from VU-mode, a virtual instr

[PATCH] target/riscv: Fix mcycle/minstret increment behavior

ff-by: Xu Lu --- target/riscv/csr.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fde7ce1a5336..c50a33397c51 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -907,11 +907,11 @@ static int write_mhpmcou