Please someone review this patch.
Thanks,
Xin
On Thu, Feb 5, 2015 at 2:04 PM, Xin Tong wrote:
> I am planning to implement support for Intel RTM. similar to what is
> done for PowerPC. we can default to fault (transaction abort) to the
> fallback code path. Would like to check in this
Hi
I would like to do GSOC this summer. The project i have in mind is to
implement a set of facilities to make implementing Hardware
transactional memory (HTM) easier in QEMU.
HTM has become available in many architecture supported by QEMU, e.g.
i386, PowerPC, etc. Currently, necessary memory tra
I am wondering why QEMU requires host CPU to support a feature for a
emulated CPU to support the same feature. say i want to support intel
transactional memory. I put the CPUID_7_0_EBX_RTM flag in the haswell
cpu feature list. However, why do i need to put the same flag into
TCG_7_0_EBX_FEATURES in
Intel Restricted Transactional Memory triggers an undefined opcode
exception when EAX=7&EBX=0 [bit 11] is not set. I am wondering where
one should check this to raise an EXCP06_ILLOP exception ?
I think adding something to the hflags and check at translation time
would be enough, would like to con
On Thu, Feb 5, 2015 at 5:52 PM, Richard Henderson wrote:
> On 02/04/2015 09:09 PM, Patrick Williams III wrote:
>>>I think one possible way is to clear the software tlb on entry to the
>>>transaction and disable (not install any translations) the software
>>>TLB till the end of the transaction.
>>>
Is there a decoding bug here ? would not stgi and vmfunc both fall
into the case 4: /* STGI */ ? And it seems case 4 is only handling
STGI.
// CHECK: stgi
// CHECK: encoding: [0x0f,0x01,0xdc]
// CHECK: vmfunc
// CHECK: encoding: [0x0f,0x01,0xd4]
case 2: /* lgdt */
case 3: /* lid
nal memory. compiled with
> Intel ICC 15.0 as well as GCC 4.8. This test case can be used to test
> intel RTM support in the target-i386 frontend.
>
> Signed-off-by: Xin Tong
>
> diff --git a/tests/tcg/test-intelrtm.c b/tests/tcg/test-intelrtm.c
> new file mode 100644
> index
If i want to implement Intel X86 hardware transactional memory (HTM) in
QEMU. what would be a good way to track the memory accesses.
I think one possible way is to clear the software tlb on entry to the
transaction and disable (not install any translations) the software TLB
till the end of the tra
Hi
I am emulating a UART serial device with QEMU. the guest OS can print to
the serial port without a problem. but how can i write to the UART serial
port. I tried to use the -serial pty backend and did not work.
i.e.
xintong1@fxilab139:$ echo 1 > /dev/pts/21 does not raise an interrupt in
the em
p and code cache re-enter
which sum to a non-trivial amount of instructions.
https://docs.google.com/spreadsheets/d/1sR7XFpVn4qCAJuU4oTOMIezvEo1WTE7riRPhT6xxUtg/edit?usp=sharing
Thanks,
Xin
On Thu, Sep 4, 2014 at 10:36 AM, Xin Tong wrote:
> Hi
>
> I would like to implement a well
Hi
I would like to implement a well known indirect branch optimization named
Polymorphic Inline Caching (PIC) in QEMU. PIC relies on software
speculation on the likely target of the indirect branch to speed up its
dispatch.
Currently, QEMU generates a EOB (end of block) after indirect branches an
where can i find most recent correctness and performance #s for QEMU ? are
there any organizations running these and making their data available
online ?
Thanks,
Xin
Thank you. Peter. sorry for forgetting about the patch for so long.
Xin
On Mon, Sep 1, 2014 at 1:19 PM, Peter Maydell
wrote:
> On 14 August 2014 01:09, Xin Tong wrote:
> > someone please reviews the patch when have time.
>
> Thanks; reviewed and applied to master. Apologies f
someone please reviews the patch when have time.
Thanks a lot,
Xin
On Mon, Aug 4, 2014 at 8:37 PM, Xin Tong wrote:
> Sorry for the absence. Forgot the patch in submission till then. I rebased
> the patch to the newest QEMU git repository and retook the performance
> improvement dat
Sorry for the absence. Forgot the patch in submission till then. I rebased
the patch to the newest QEMU git repository and retook the performance
improvement data. Please review when have time.
Xin
On Mon, Aug 4, 2014 at 8:35 PM, Xin Tong wrote:
> QEMU system mode page table walks
fluctuations, the performance
improvement is very significant and by no means in the range of
noises.
Signed-off-by: Xin Tong
---
cputlb.c| 31 ++-
include/exec/cpu-defs.h | 9 +++--
softmmu_template.h | 43
can anyone provide further review to this patch please ?
Thank you,
Xin
On Mon, Feb 3, 2014 at 9:50 AM, Eric Blake wrote:
> On 02/03/2014 08:18 AM, Xin Tong wrote:
>> This patch adds a victim TLB to the QEMU system mode TLB.
>>
>> Changes from PATCH v3.
>> 1. updated
s in the range of
noises.
Signed-off-by: Xin Tong
---
cputlb.c| 31 ++-
include/exec/cpu-defs.h | 9 +++--
include/exec/softmmu_template.h | 41 +
3 files changed, 74 insertions(+), 7 delet
February 2014 19:01, Xin Tong wrote:
>> I am getting some compilation errors while stringnifying the
>> ADDR_READ, addr_write.
>>
>> function helper_be_ldq_cmmu
>>
>> if (!VICTIM_TLB_HIT(ADDR_READ)) {
>>
&
e/xtong/qemu/include/exec/softmmu_template.h: In function
'helper_be_ldq_cmmu':
/home/xtong/qemu/include/exec/softmmu_template.h:266: error: expected
identifier before string constant
Xin
On Sun, Feb 2, 2014 at 12:33 PM, Peter Maydell wrote:
> On 2 February 2014 18:27, Xin Tong wrote:
>
On Sun, Feb 2, 2014 at 10:19 AM, Peter Maydell wrote:
> On 2 February 2014 15:15, Xin Tong wrote:
>> Hi Peter
>>
>> Thank you for your reviews , i have 2 questions.
>>
>> On Sat, Feb 1, 2014 at 4:14 PM, Peter Maydell
>> wrote:
>>> On 28 Januar
Hi Peter
Thank you for your reviews , i have 2 questions.
On Sat, Feb 1, 2014 at 4:14 PM, Peter Maydell wrote:
> On 28 January 2014 17:31, Xin Tong wrote:
>> This patch adds a victim TLB to the QEMU system mode TLB.
>>
>> QEMU system mode page table walks are expensive.
before. But i've learned from the mistakes and will try to
have future patch submission done according to guidelines.
Best Regards,
Xin
On Wed, Jan 29, 2014 at 10:03 AM, Xin Tong wrote:
> can someone please review this patch ?
>
> Thank you,
> Xin
>
> On Tue, Jan 28, 201
can someone please review this patch ?
Thank you,
Xin
On Tue, Jan 28, 2014 at 11:31 AM, Xin Tong wrote:
> This patch adds a victim TLB to the QEMU system mode TLB.
>
> QEMU system mode page table walks are expensive. Taken by running QEMU
> qemu-system-x86_64 system mode on Intel
ring
Although there are measurement fluctuations, the performance
improvement is very significant and by no means in the range of
noises.
Signed-off-by: Xin Tong
---
cputlb.c| 50 -
include/exec/cpu-defs.h | 12 ++---
include/
Richard. I am sorry. I thought the patch submitter put review-bys
themselves. How do i get a reviewed-by ?
Xin
On Thu, Jan 23, 2014 at 3:47 PM, Richard Henderson wrote:
> On 01/23/2014 11:49 AM, Xin Tong wrote:
>> Reviewed-by: Richard Henderson
>> Signed-off-by: Xin Tong
>
Hi Max
Thank you for taking the time to review my patch
On Thu, Jan 23, 2014 at 2:44 PM, Max Filippov wrote:
> Hi Xin,
>
> On Thu, Jan 23, 2014 at 11:49 PM, Xin Tong wrote:
>
> [...]
>
>> diff --git a/cputlb.c b/cputlb.c
>> index b533f3f..03a048a 100644
>&
Attaching data in excel which could not be sent with the patch at the same time.
On Thu, Jan 23, 2014 at 1:49 PM, Xin Tong wrote:
> This patch adds a victim TLB to the QEMU system mode TLB.
>
> QEMU system mode page table walks are expensive. Taken by running QEMU
> qemu-system-x
.
Reviewed-by: Richard Henderson
Signed-off-by: Xin Tong
---
cputlb.c| 50 +-
include/exec/cpu-defs.h | 16 ++---
include/exec/exec-all.h | 2 ++
include/exec/softmmu_template.h | 80
On Thu, Jan 23, 2014 at 5:23 AM, Alex Bennée wrote:
>
> trent.t...@gmail.com writes:
>
>> This patch adds a victim TLB to the QEMU system mode TLB.
>>
>> QEMU system mode page table walks are expensive. Taken by running QEMU
>> qemu-system-x86_64 system mode on Intel PIN , a TLB miss and walking a
the title of "[Qemu-devel] [PATCH v2] cpu:
implementing victim TLB for QEMU system emulated TLB" and with the
changes from both of the patches ?
Xin
On Wed, Jan 22, 2014 at 3:55 PM, Richard Henderson wrote:
> On 01/22/2014 06:48 AM, Xin Tong wrote:
>> +#define TLB_XOR_SWAP(X,
Richard:
That is very intelligient way to support AVX. I believe Bochs uses
similar technique.
On Wed, Jan 22, 2014 at 2:19 PM, Richard Henderson wrote:
> On 01/22/2014 11:35 AM, Xin Tong wrote:
>> It seems that BOCHS have AVX instructions support in interpreter. I am
>> t
move some of the instructions into TCG JITted
code ?
Also, it would be desirable to use the MMX/SSE structures and
functions that already exist in QEMU target-i386/translate.c
please comment.
Xin
On Wed, Jan 22, 2014 at 11:35 AM, Paolo Bonzini wrote:
> Il 22/01/2014 17:27, Xin Tong ha scri
would there be any memory ordering issue ? what if the host processor
has a more relaxed memory ordering then the guest. maybe memset with
membarriers in between.
Xin
On Wed, Jan 22, 2014 at 1:06 PM, Richard Henderson wrote:
> On 01/22/2014 10:58 AM, Peter Maydell wrote:
>> In theory we could ju
I have submitted a patch to the QEMU devel list on implementing a
victim tlb in QEMU. i should have you 2 CC'ed on the patch email so
that you can help review the patch in case no one is reviewing it. The
name of the patch is
[Qemu-devel] [PATCH] cpu: implementing victim TLB for QEMU system emulate
Intel AVX instructions have been out for some time since sandy-bridge.
Is there value to support it in QEMU. I am thinking abut a google
summer of code this year to bring support for AVX/AVX2.0 to QEMU.
Xin
On Wed, Nov 27, 2013 at 8:12 PM, Richard Henderson wrote:
> On 11/27/2013 08:41 PM, Xin Tong wrote:
>> I am trying to implement a out-of-line TLB lookup for QEMU softmmu-x86-64 on
>> x86-64 machine, potentially for better instruction cache performance, I have
>> a
>>
, the
implemented victim TLB is architecture independent and is expected to
benefit other architectures in QEMU as well.
Although there are measurement fluctuations, the performance
improvement are very significant and by no means in the range of
noises.
Signed-off-by: Xin Tong
---
cputlb.c
the fact that the primary TLB is directly mapped and
suffer from conflict misses. I have this implemented on QEMU trunk and
would like to contribute this back to QEMU. Where should i start ?
Xin
On Tue, Dec 17, 2013 at 8:22 PM, Xin Tong wrote:
> why is QEMU TLB organized based on the modes, e.g.
I see QEMU TLB is organized by access modes, e.g. in emulating X86,
there are 3 modes.
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_MODE2_SUFFIX _ksmap /* Kernel with SMAP override */
Why can not QEMU have a global TLB for all modes ?
Xin
?
Thank you,
Xin
On Tue, Dec 17, 2013 at 10:52 PM, Xin Tong wrote:
> On Sun, Dec 8, 2013 at 2:54 AM, Xin Tong wrote:
>>
>>
>>
>> On Thu, Nov 28, 2013 at 8:12 AM, Lluís Vilanova wrote:
>>>
>>> Xin Tong writes:
>>>
>>> > Hi LIuis
&
On Sun, Dec 8, 2013 at 2:54 AM, Xin Tong wrote:
>
>
>
> On Thu, Nov 28, 2013 at 8:12 AM, Lluís Vilanova wrote:
>>
>> Xin Tong writes:
>>
>> > Hi LIuis
>> > we can probably generate vector intrinsics using the tcg, e.g. add
>> > support
On Thu, Dec 12, 2013 at 1:07 PM, Xin Tong wrote:
> see questions below.
>
> On Tue, Dec 10, 2013 at 12:25 AM, Alex Bennée wrote:
>>
>> trent.t...@gmail.com writes:
>>
>>> Does anyone have profiles on how much time QEMU spends in translating
>>>
see questions below.
On Tue, Dec 10, 2013 at 12:25 AM, Alex Bennée wrote:
>
> trent.t...@gmail.com writes:
>
>> Does anyone have profiles on how much time QEMU spends in translating
>> instructions. QEMU does not have a baseline interpreter nor does it
>> translate on trace-granularity. so i ima
ber 2013 06:36, Xin Tong wrote:
> > Is it possible for QEMU to obviate some of the translations by attaching
> a
> > signature (e.g. a hash) with every translated basic block and try to
> reuse
> > translated basic block based on the signature as much as possible ?
>
On Thu, Nov 28, 2013 at 8:12 AM, Lluís Vilanova wrote:
> Xin Tong writes:
>
> > Hi LIuis
> > we can probably generate vector intrinsics using the tcg, e.g. add
> support to
> > tcg to emit vector instructions directly in code cache
>
> There was some discus
Does anyone have profiles on how much time QEMU spends in translating
instructions. QEMU does not have a baseline interpreter nor does it
translate on trace-granularity. so i imagine QEMU must spend quite a bit
of time translating instructions.
Is it possible for QEMU to obviate some of the trans
On Thu, Nov 28, 2013 at 8:12 AM, Lluís Vilanova wrote:
> Xin Tong writes:
>
> > Hi LIuis
> > we can probably generate vector intrinsics using the tcg, e.g. add
> support to
> > tcg to emit vector instructions directly in code cache
>
> There was some discus
I am wondering whether it is possible to propose project in QEMU google
summer of code as a student ? I have some ideas regarding TLB emulation in
system mode and would like to find a mentor to do a gsoc for it.
Thank you,
Xin
On Wed, Nov 27, 2013 at 6:12 PM, Richard Henderson wrote:
> On 11/27/2013 08:41 PM, Xin Tong wrote:
> > I am trying to implement a out-of-line TLB lookup for QEMU
> softmmu-x86-64 on
> > x86-64 machine, potentially for better instruction cache performance, I
> have
I am wondering what are some of the use cases for QEMU as an instruction
set emulator(not KVM). I know QEMU is used for the android emulator and
QEMU is used to host a few cycle accurate simulators ?
what else ?
Thank you,
Xin
always used to index into the TLB, i.e. (X & (CPU_TLB_SIZE
-1)).
Thank you
Xin
On Wed, Nov 27, 2013 at 5:12 AM, Lluís Vilanova wrote:
> Xin Tong writes:
>
> > I am trying to implement a out-of-line TLB lookup for QEMU
> softmmu-x86-64 on
> > x86-64 machine, potential
I am trying to implement a out-of-line TLB lookup for QEMU softmmu-x86-64
on x86-64 machine, potentially for better instruction cache performance, I
have a few questions.
1. I see that tcg_out_qemu_ld_slow_path/tcg_out_qemu_st_slow_path are
generated when tcg_out_tb_finalize is called. And when a
Hi
I would like to know where i get can 32bit ARM image with appropriate
network driver.
thank you,
Xin
I am writing code to trace all the branches in ARM, i would like to confirm
with people whether I am doing this correctly.
I put in code in gen_jmp to trace all the branches that are taken, afaik,
the gen_jmp gets called when an unconditional branch is JITed or in the
s->condlabel of conditional
you are right richard. it turns out i am generating too many tcg opcode in
the frontend, such that OPC_BUF_SIZE is too small.
Thank you
Xin
On Mon, Nov 4, 2013 at 8:18 AM, Richard Henderson wrote:
> On 11/03/2013 05:22 AM, Xin Tong wrote:
> > I am running QEMU user mode, but i hit
I am running QEMU user mode, but i hit a SIGSEV. It seems that tcg_malloc
returns invalid address.
The stack trace looks like this. and the s->nb_temps looks ok as well. I
also turned on DEBUG_TCGV and all the TCGV_X uses are good.
(gdb) bt
#0 0x75db0866 in ?? () from /lib/x86_64-linux-g
Hi.
I would like to trace all the executed instruction PC in QEMU ARM. Because
ARM has conditional execution, we do not know whether an instruction will
execute or not at translation time. Therefore the PC tracing code can not
be generated before the instruction is disassembled. (i.e. before
disas
I have the code on http://code.google.com/p/qemu-trace/. I currently
have memory trace, branch trace and some special instructions traces
ready ( unverified though). we should discuss about what is the best
way to do this btw.
Xin
On Wed, Sep 12, 2012 at 10:09 AM, Xin Tong wrote:
> On Wed,
On Wed, Sep 12, 2012 at 6:14 AM, Lluís Vilanova wrote:
> Xin Tong writes:
>
>> i do not know. could be similar. I am doing architecture research. i
>> need traces of memory access for programming running under a full
>> system environment, so i wrote this.
>
>> i
i do not know. could be similar. I am doing architecture research. i
need traces of memory access for programming running under a full
system environment, so i wrote this.
i do nto seem to be able to access the linked provided from the link
you give me though.
https://projects.gso.ac.upc.edu/proj
On Tue, Sep 11, 2012 at 9:12 AM, Richard Henderson wrote:
> On 09/10/2012 08:17 PM, Xin Tong wrote:
>> I have 2 questions about TCGv.
>>
>> 1. if DEBUG is enabled on TCGv, TCGv is wrapped in a C struct. and
>> would it not be very expensive to pass TCGv by copy
I have 2 questions about TCGv.
1. if DEBUG is enabled on TCGv, TCGv is wrapped in a C struct. and
would it not be very expensive to pass TCGv by copy for all the
tcg_gen_xxx functions.i.e. tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
2. I have created some files that need to include tcg-op.h and cpu.h
I would like to know how well is the Intel VMX and AMD SVM supported in QEMU ?
Xin
On Sun, Sep 2, 2012 at 8:52 AM, Xin Tong wrote:
> On Sat, Sep 1, 2012 at 10:52 PM, Mulyadi Santosa
> wrote:
>> On Sun, Sep 2, 2012 at 2:33 AM, Xin Tong wrote:
>>> I want to detect context switches in QEMU x86_64-softmmu. one of the
>>> ideas i have is to track the
On Sat, Sep 1, 2012 at 10:52 PM, Mulyadi Santosa
wrote:
> On Sun, Sep 2, 2012 at 2:33 AM, Xin Tong wrote:
>> I want to detect context switches in QEMU x86_64-softmmu. one of the
>> ideas i have is to track the write to CR3. is this valid on QEMU (
>> i.e. are their a
I want to detect context switches in QEMU x86_64-softmmu. one of the
ideas i have is to track the write to CR3. is this valid on QEMU (
i.e. are their any cases in which the assumption could break).
Xin
On Thu, Aug 23, 2012 at 9:06 PM, 陳韋任 (Wei-Ren Chen)
wrote:
>> That might be difficult. what i did was that i disabled inlined
>> translated and push the virt/phys address into 2 new fields in the cpu
>> structure in the call out lookup. because in the callout lookup we
>> have a handle to the cpu
On Thu, Aug 23, 2012 at 7:57 PM, 陳韋任 (Wei-Ren Chen)
wrote:
>> even that. is it possible to pass host virtual out. the fast path add
>> the addend to get host virtual ? so it must be in a register, most
>> likely eax in i386. what do you think would be the best way to get
>> that out ?
>
> Take a
On Thu, Aug 23, 2012 at 8:52 AM, Peter Maydell wrote:
> On 23 August 2012 16:34, Xin Tong wrote:
>> I am emulating arm on x86. i want to track the virt and physical
>> address of last memory operation. so i put 2 fields in the CPUState
>> and make tcg_global_mem_new_i32 on t
I am emulating arm on x86. i want to track the virt and physical
address of last memory operation. so i put 2 fields in the CPUState
and make tcg_global_mem_new_i32 on them Therefore, before every
translation i generate code to save the virtual address as follow:
static inline void gen_st32(TCGv v
On Wed, Aug 22, 2012 at 8:14 PM, 陳韋任 (Wei-Ren Chen)
wrote:
>> In tcg_gen_qemu_ld8s(tmp, addr, index); a TCGv addr is passed to the
>> INDEX_op_qemu_ld8s as param and the loaded value is passed back in
>> tmp. i want to get the translated value as well. how can i do that ?
>
> IIUC, qemu_ld take
Hello
In tcg_gen_qemu_ld8s(tmp, addr, index); a TCGv addr is passed to the
INDEX_op_qemu_ld8s as param and the loaded value is passed back in
tmp. i want to get the translated value as well. how can i do that ?
one way i can think of right now is to modify the INDEX_op_qemu_ld8s
and make it take
Does QEMU have all the supports to boot android on arm ?
Xin
yes, there is a measurement published in KVM conference.
http://www.linux-kvm.org/wiki/images/e/ea/2010-forum-mtosatti_walkthrough_entry_exit.pdf
Xin
On Thu, Jul 5, 2012 at 4:51 AM, wrote:
> Hi Xin Tong,
>
> Do you get any estimation on that?
>
> Regards,
> chenwj
>
It is a pity that QEMU does not outline the TLB lookup code. I do not
know how much impact the inlined TLB code has due to icache misses...
Another benefit one gets from outlined TLB code is that it is much
easier to gather the amount of time spent in the TLB. one can just
profile QEMU and count u
On Fri, Jun 22, 2012 at 3:28 AM, 陳韋任 (Wei-Ren Chen)
wrote:
> Hi Xin Tong,
>
> O.K., after studying KVM a little bit, I just give you my 2 cents. :)
>
> On Fri, Jan 20, 2012 at 12:12:00AM -0500, Xin Tong wrote:
>> I am wondering the possibilities of using the nested pa
In QEMU x86, TB translation flags are set up when the TB is allocated.
what will happen if the translation flags are modified by one
instruction in the translation block ? will the translation block be
terminated right there.
For example, there is a code32 flag which is set to the value of
(flags
I am looking at how arithemetic and logic operations are emulated in
x86. it came to my attention that only xor reg_a, reg_a updates the cc
value. what about other operations ? also there are a new cc value and
an old cc value ? why is that ?
Thanks
Xin
i got it working with libguestfs. libguestfs is awesome at
manipulating guest VM images.
Xin
On Tue, Apr 24, 2012 at 4:45 AM, Mulyadi Santosa
wrote:
> On Tue, Apr 24, 2012 at 02:09, Xin Tong wrote:
>> I am not too sure what you mean by raw image. what i have is an *.img
>&g
so it is not possible to have a longjmp happening while an emulated
cpu is in the middle of translating code ( i.e. in frontend or tcg).
Xin
On Mon, Apr 23, 2012 at 12:02 PM, Peter Maydell
wrote:
> On 23 April 2012 01:06, Xin Tong wrote:
>> QEMU uses this very hard to understand s
On Mon, Apr 23, 2012 at 4:38 AM, Kevin Wolf wrote:
> Am 22.04.2012 18:37, schrieb Xin Tong:
>> i have an OS image that does not have network drivers. are there any
>> other ways to copy a benchmark onto the os image ?
>
> If it is a raw image you can use kpartx to get bloc
ahhh. got it working for one of the images. the other image, when i
try to boot it up. i do not see /dev/cdrom in it. however, when i go
to the qemu monitoring window, i do see ide1-cd0 : type:cdrom,
removeable=1 ...
Any suggestions ?
Thanks
Xin
On Mon, Apr 23, 2012 at 1:32 PM, Xin Tong
i also issued the change ide-cd0
/home/xtong/qemu/qemu-0.14.1/x86_64-softmmu/ubuntu-11.10-server-amd64.iso
in the qemu montoring tool. where can i find the inserted cd rom in
the guest os ?
Xin
On Mon, Apr 23, 2012 at 1:17 PM, Xin Tong wrote:
> I tried to insert a cdrom using this command.
>>>> wrote:
>>>>> On Sun, Apr 22, 2012 at 5:37 PM, Xin Tong
>>>>> wrote:
>>>>>> i have an OS image that does not have network drivers. are there any
>>>>>> other ways to copy a benchmark onto the os image ?
>>&g
QEMU uses this very hard to understand setjmp and longjmp to handle
asynchronous interrupt. what i do not understand is that say one of
the process is doing a context switching in the guest os. tlb_flush
gets called, what if in the middle of tlb_flush, an interrupt comes in
( longjmp executed ). d
i have an OS image that does not have network drivers. are there any
other ways to copy a benchmark onto the os image ?
Thanks
Xin
On Mon, Apr 16, 2012 at 10:51 PM, 陳韋任 wrote:
>> what does the inline sequence look like ? what kind of things (other
>> than refill tlb) performed in callout but not the inlined sequence ?
>
> What do you mean by the inline sequence, the host binary? If so,
>
> ---
> 0xe86c8
> mov_i32 tmp2
On Sat, Apr 21, 2012 at 3:06 AM, Blue Swirl wrote:
> On Fri, Apr 20, 2012 at 04:25, Xin Tong wrote:
>> On Thu, Apr 19, 2012 at 6:56 PM, Xin Tong wrote:
>>> On Thu, Apr 19, 2012 at 1:03 PM, Blue Swirl wrote:
>>>> On Thu, Apr 19, 2012 at 01:55, Xin Tong wrote:
&g
On Thu, Apr 19, 2012 at 6:56 PM, Xin Tong wrote:
> On Thu, Apr 19, 2012 at 1:03 PM, Blue Swirl wrote:
>> On Thu, Apr 19, 2012 at 01:55, Xin Tong wrote:
>>> but should not the address be within 1 - 4G-1 even with PAE. is not
>>> the PAE just using 64bits addresses a
On Thu, Apr 19, 2012 at 1:03 PM, Blue Swirl wrote:
> On Thu, Apr 19, 2012 at 01:55, Xin Tong wrote:
>> but should not the address be within 1 - 4G-1 even with PAE. is not
>> the PAE just using 64bits addresses as supposed to 32 bit ? what does
>> the physical address bigg
:03 PM, Blue Swirl wrote:
> On Wed, Apr 18, 2012 at 01:28, Xin Tong wrote:
>> I am reading how qemu refill TLB working.
>>
>> target-i386/helper.c
>>
>> pte = pte & env->a20_mask;
>>
>> /* Even if 4MB pages, we map only one 4KB pag
I am reading how qemu refill TLB working.
target-i386/helper.c
pte = pte & env->a20_mask;
/* Even if 4MB pages, we map only one 4KB page in the cache to
avoid filling it too fast */
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
paddr = (pte & TARGET_PAGE_MASK)
that is possible. but if that is the case, why not split the tlb
walking and the tlb fill ? can anyone please confirm ?
Xin
2012/4/16 陳韋任 :
>> > If TLB miss, it will call something like __ldb_mmu (b). __ldb_mmu will try
>> > to
>> > walk guest page table, then fill TLB entry if page table hit,
On Mon, Apr 16, 2012 at 10:51 PM, 陳韋任 wrote:
>> what does the inline sequence look like ? what kind of things (other
>> than refill tlb) performed in callout but not the inlined sequence ?
>
> What do you mean by the inline sequence, the host binary? If so,
>
> ---
> 0xe86c8
> mov_i32 tmp2
it seems qemu has an inlined sequence to walk the tlb. if that fails,
it does a call out.
tcg_out_tlb_load(s, addrlo_idx, mem_index, s_bits, args,
label_ptr, offsetof(CPUTLBEntry, addr_write));
/* TLB Hit. */
tcg_out_qemu_st_direct(s, data_reg, data_reg2,
I am wondering what the solution in qemu is if the guest architecture
has a stronger memory ordering requirement than the host archiecture ?
memory fences ?
Thanks
Xin
can you show me where these threads get created in the qemu code ?
Thanks
Xin
On Tue, Feb 7, 2012 at 5:25 AM, Stefan Hajnoczi wrote:
> 2012/2/7 陳韋任 :
>> Hi Stefan,
>>
>> Thanks for the explanation. :)
>>
>>> > Qemu 1.0 enable IO thread by default, I think that's why you can see
>>> > ther
anyone cares to answer. I appreciate it.
Thanks
Xin
On Sat, Jan 28, 2012 at 5:17 PM, Xin Tong wrote:
> I am investigating what longjmp is used for in qemu.
>
> longjmp is used in a couple of places.
>
> 1.
> void cpu_loop_exit(void)
> {
> env->current_t
I am investigating what longjmp is used for in qemu.
longjmp is used in a couple of places.
1.
void cpu_loop_exit(void)
{
env->current_tb = NULL;
longjmp(env->jmp_env, 1);
}
cpu_loop_exit is called when there is an interrupt_request or exit_request
pending
2.
void cpu_resume_from_signa
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