ate PC after each
guest instruction, which cost too much). So I guess you can check follow
the control flow and see when/where QEMU get the correct PC, then call your
exception handler instead, not QEMU's one.
HTH,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Informat
> I've examined the alarm timmer, this timer is used to interrupt the
> execution of VCPUs to handle interruptions.
IIRC, alarm timer will interrupt VCPU to execute the next one.
You can check where QEMU register the alarm timer, and see how it
works.
Regards,
chenwj
--
Wei-Re
roject.
>
> I am looking for any comment about the difficulty and the content of
> the project, and also about my chances to be accepted if i apply for.
As a libvirt user, I would give it a "+1". Currently I have to use
`arp -n` on the host to checkout VM's ip.
Regards,
ch
> you're right, seems the word 'optimize' is not good here.
> but what should I use?
> you know, even compiler like gcc will use -O for code optimization.
"translate: code cleanup in gen_intermediate_code_internal" would be
better, I think. :)
Regards,
chenw
if they benefit little
> in performance?
IMO, if you are saying the patch can improve performance, then
you should run benchmark to convince others. If your patch is trying
to make code clear, then "optimize" might not be a good term to describe
your patch.
Regards,
chenwj
--
Hi liguang,
On Tue, Apr 09, 2013 at 04:21:10PM +0800, li guang wrote:
> 在 2013-04-09二的 10:11 +0200，Paolo Bonzini写道：
> > Il 09/04/2013 10:05, 陳韋任 (Wei-Ren Chen) ha scritto:
> > > Hi liguang,
> > >
> > > Just to be curious, how much performance improvement
On Tue, Apr 09, 2013 at 10:11:37AM +0200, Paolo Bonzini wrote:
> Il 09/04/2013 10:05, 陳韋任 (Wei-Ren Chen) ha scritto:
> > Hi liguang,
> >
> > Just to be curious, how much performance improvement this patch can get?
>
> I think zero. It is indeed making the code
;
> gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
> @@ -15678,9 +15678,9 @@ done_generating:
> *tcg_ctx.gen_opc_ptr = INDEX_op_end;
> if (search_pc) {
> j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
> -lj++;
> -while (lj <= j)
> -tcg_ctx.gen_opc_instr_start[lj++] = 0;
> +while (++lj <= j) {
> +tcg_ctx.gen_opc_instr_start[lj] = 0;
> +}
> } else {
> tb->size = ctx.pc - pc_start;
> tb->icount = num_insns;
> --
> 1.7.2.5
>
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
r website (mention no support for SDL,
for example).
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
glib-2.0/include
> -I/usr/local/include -MMD -MP -MT target-i386/kvm-stub.o -MF
> target-i386/kvm-stub.d -O2 -D_FORTIFY_SOURCE=2 -g -c -o
> target-i386/kvm-stub.o /home/todd/git/sw/3rdParty/qemu/target-i386/kvm-stub.c
Is it possible to update your GCC, or try to use clang?
HTH,
chenwj
en program point. The
- x86 target uses it to improve the condition codes optimisation.
+ x86 guest uses it to improve the condition codes optimisation.
--
1.7.12.3
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
Thanks, Peter.
On Thu, Mar 14, 2013 at 09:03:15AM +, Peter Maydell wrote:
> On 14 March 2013 08:06, 陳韋任 (Wei-Ren Chen) wrote:
> > In TCG, "target" means the host architecture for which TCG generates
> > the code. Using "guest" rather than
In TCG, "target" means the host architecture for which TCG generates
the code. Using "guest" rather than "target" to make the document more
consistent.
Signed-off-by: Chen Wei-Ren
---
tcg/README | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/tcg/README b/tcg/
On Fri, Mar 08, 2013 at 11:13:24AM +0100, Stefan Hajnoczi wrote:
> On Fri, Mar 08, 2013 at 05:29:29PM +0800, Peter Maydell wrote:
> > On 8 March 2013 17:21, Stefan Hajnoczi wrote:
> > > On Thu, Mar 07, 2013 at 11:33:01AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> > >> I
On Thu, Mar 07, 2013 at 06:57:19PM +0800, yue-kvm wrote:
> hi stefan:
>
> [root@kvm ~]# qemu-img -V
> qemu-img version 0.12.1, Copyright (c) 2004-2008 Fabrice Bellard
Hrm..., 0.12 is too old, why don't you use newer version?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Com
me/dec: OK
/i386/rtc/alarm/interrupt: OK
...
Developers should add their test into ${QEMU_SRC}/tests . Am I right?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
tmmu/qemu-system-arm -test ?
> qemu-system-arm: -test: invalid option
From Makefile.target, qtest is built when you build softmmu target.
I guess there is no need to add "--enable-qtest" option. However, I
don't know how to run qtest...
Stefan (Cc'ed), I think we should cleanup QT
In TCG, "target" means the host architecture for which TCG generates the
code. Using "guest" rather than "target" to make the document more consistent.
Signed-off-by: Chen Wei-Ren
---
tcg/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/README b/tcg/README
index 9
On Wed, Mar 06, 2013 at 11:47:58AM +0800, Peter Maydell wrote:
> On 6 March 2013 11:30, 陳韋任 (Wei-Ren Chen) wrote:
> > While searching for QEMU SIMD issues, I found there was a paper presented
> > in 2011 [1], and the source code is also public on [2]. However, it seems
> >
df
[2] http://tima-sls.imag.fr/www/research/qemu/simd-qemu/
[3] http://lists.gnu.org/archive/html/qemu-devel/2011-03/msg02065.html
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage:
ill a good default? I am just wondering if those
boards with little memory still are major user of QEMU? :)
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
easurement, I
guess. The problem is how you get the time spent is the code cache. I
guess you have to spot where QEMU jump into the code cache, and
when/where it leave the code cache. Then insert your profiling code
there.
HTH,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Infor
can install that packages with yum, then download and build
it yourself. You can download glib from here [2].
Regards,
chenwj
[1] http://wiki.xen.org/wiki/QEMU_Upstream
[2] http://ftp.gnome.org/pub/gnome/sources/glib/2.34/
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science
qemu-upstream
> so that fully conforming to the CODING_STYLE is not a little work, if anyone
> is interested in the feature, welcome to join in the work.
That might be a hint that you need to split your patch into smaller
pieces. :)
Regards,
chenwj
[1] http://wiki.qemu.org/Download
--
W
or *mon)
> int64_t qemu_time;
> int64_t dev_time;
>
> -static void do_info_profile(Monitor *mon)
> +static void do_info_profile(Monitor *mon, const QDict *qdict)
> {
> int64_t total;
> total = qemu_time;
> @@ -1816,7 +1816,7 @@ static void do_info_profile(Monito
When tb_remove was first commited at fd6ce8f6, there were three different
calls pass different names to offsetof. In current codebase, the other two
calls are replaced with tb_page_remove. There is no need to have a general
tb_remove. Omit passing the third parameter and using tb1->phys_hash_next
, env->active_tc.PC, env->CP0_EPC, name);
}
...
}
Maybe we can do this way?
---
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 31602ac..507a213 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -616,9 +616,9 @@ enum {
EXCP_DSPDIS,
EXCP_LAST = EXCP_DSPD
On Tue, Dec 18, 2012 at 05:37:53PM +0100, Stefan Hajnoczi wrote:
> On Wed, Nov 21, 2012 at 07:52:48AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> > When tb_remove was first commited at fd6ce8f6, there were three different
> > calls pass different names to offsetof. In current codebase
ping? :-)
On Tue, Dec 11, 2012 at 12:15:55AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> From the discussion on the ML [1], the exception limit defined by
> magic number 0x100 is actually EXCP_SC defined in cpu.h. Replace the
> magic number with EXCP_SC. Remove "#if 1 .. #endif" as
On Thu, Dec 13, 2012 at 08:22:06PM +0800, Pan Xueshu wrote:
> Because it has been disabled to create account on the wiki page. Thanks
> very much!
From IRC, I guess kwolf already did this for you?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information S
l still show an
> old email address. Most email addresses have a limit life time.
Well... Just let him fix his mail address (he want it in the source
code). Maybe we can discuss if we want the mail address in the code
while reviewing new coming patch next time. ;)
Regards,
chenwj
--
Wei-Re
From the discussion on the ML [1], the exception limit defined by
magic number 0x100 is actually EXCP_SC defined in cpu.h. Replace the
magic number with EXCP_SC. Remove "#if 1 .. #endif" as well.
[1] http://lists.gnu.org/archive/html/qemu-devel/2012-11/msg03080.html
Signed-off-by: Chen Wei-Ren
d.h:
> > No such file or directory
> >
> > (though for some reason not as a fatal error).
>
> Bizzare.
>
> Out of curiosity, does llvm ship a cpuid.h? Or am I going to be
> better off not relying on that header at all?
I don't think LLVM ship cpuid.h.
27;t above helper function be called from the code cache?
The 3rd argument of do_raise_exception means if the exception comes
from code cache or not, iiuc. Is it correct to put zero here?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sini
[CC'ed qemu-trivial]
ping?
On Wed, Nov 21, 2012 at 07:52:48AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> When tb_remove was first commited at fd6ce8f6, there were three different
> calls pass different names to offsetof. In current codebase, the other two
> calls are replaced with
, it my bring a error.
Why not use `git send-mail`? See more details on
http://wiki.qemu.org/Contribute/SubmitAPatch
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
ed locally, and that your
> > change to just returning bool broke this. And in this version
> > of the patch there is still exactly the same problem.
>
> why broke?
> this function just ask if breakpoint 'i' was enable,
> so we answer enabled or not? 2 simple cases, any problem?
I don't read this patch from the starting. But Peter, do you mean
the return value matters here? I see the original version compares
the return value with 0x1, do you mean we *need* this comparsion here?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
se_exception_err(cpu, exception, pc);
> +}
Please change your subject into "[PATCH v2] ..." so that others will
notice this is a new version patch. See [1] for more detail. Also, you
still doesn't address v1's comment. Why you put both do_raise_exception_err
and do_raise
es all nested paths, so it must come last
No objection here. But will we remove this option when GCC fix this pr
or we just leave it there? If we're going to remove it in the future,
better keep a note on the release change log or somewhere else.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Comput
it of old broken systems.
>
> It isn't that simple. It's Fedora 17 with gcc 4.7.2 which runs oom
> while compiling translate.c
Even apply Peter's suggestion? Do all gcc 4.7.2 on various platform
have the same problem, or it only happen on Fedora 17.
Regards,
chenwj
--
Wei-Ren
On Sun, Nov 25, 2012 at 10:47:00AM +, Peter Maydell wrote:
> On 25 November 2012 07:50, 陳韋任 (Wei-Ren Chen)
> wrote:
> > ping?
>
> This is v1 of the patch, you've sent a v2 and should be pinging that
> instead... Also (a) it won't go in before 1.3 release n
ping?
On Tue, Nov 20, 2012 at 12:41:03PM +, Peter Maydell wrote:
> On 20 November 2012 12:30, 陳韋任 (Wei-Ren Chen)
> wrote:
> > When tb_remove was first commited at fd6ce8f6, there were three different
> > calls pass different names to offsetof. In current codeb
,
...
{
...
#if 1
if (exception < 0x100)
qemu_log("%s: %d %d\n", __func__, exception, error_code);
#endif
...
}
Anyone can help confirm this, stated in what spec? Also, do we
need "#if 1 .. #endif"? Thanks for help. =]
Regards,
chenwj
--
Wei-Ren Chen
(exception < 0x100)
> > +qemu_log("%s: %d\n", __func__, exception);
> > +#endif
>
> Stray debug tracing?
target-mips/op_helper.c also has such "#if 1 .. #endif".
Should we remove it?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Ins
void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t exception);
>
> +void QEMU_NORETURN do_raise_exception_err(OpenRISCCPU *cpu,
> + uint32_t exception,
> + uintptr_t pc);
> +void QEMU_NORETURN do_raise_exception(OpenRISCCPU *
h, what I hope
> is a correct, list of names against faces...
>
> http://www.linux-kvm.org/static/kvm-forum-2012-barcelona-team-photo.html
Great!
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-37
,
+SD32 = 0x36, /* MIPS64 */
+LD32 = 0x37, /* MIPS64 */
/* 0x38 and 0x39 are reserved */
RES_38 = 0x38,
--
1.7.12.3
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http
Hi Johnson,
My bad. Will resend pacth later. ;)
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
Current QEMU MIPS POOL32AXF encoding comes from microMIPS32
and microMIPS32 DSP. Add comment here to help reading.
Signed-off-by: Chen Wei-Ren
---
v2: Correct commit message formatting
target-mips/translate.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/target-mips/
c & ~TARGET_PAGE_MASK);
h = tb_phys_hash_func(phys_pc);
-tb_remove(&tb_phys_hash[h], tb,
- offsetof(TranslationBlock, phys_hash_next));
+tb_hash_remove(&tb_phys_hash[h], tb);
/* remove the TB from the page list */
if (tb->page_addr[0] != page_addr) {
--
1.7.
When tb_remove was first commited at fd6ce8f6, there were three different
calls pass different names to offsetof. In current codebase, the other two
calls are replaced with tb_page_remove. There is no need to have a general
tb_remove. Omit passing the third parameter and using tb1->phys_hash_next
ping?
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
ping?
On Fri, Nov 16, 2012 at 10:29:47AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> Hi all,
>
> Current QEMU MIPS POOL32AXF encoding comes from microMIPS32
> and microMIPS32 DSP. Add comment here to help reading.
>
> Please review, thanks.
>
> Regards,
> chenwj
>
On Fri, Nov 16, 2012 at 02:59:30PM +0100, Stefan Hajnoczi wrote:
> On Fri, Nov 16, 2012 at 10:29:47AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> > Current QEMU MIPS POOL32AXF encoding comes from microMIPS32
> > and microMIPS32 DSP. Add comment here to help reading.
> >
> &
> Please send this through Aurelian as maintainer for target-mips/. The
> discussion on previous the thread show this isn't qemu-trivial material
> :).
O.K., I'll remove this from qemu-trivial if I need to send revision
next time. Thanks, Stefan.
Regards,
chenwj
--
Hi all,
Current QEMU MIPS POOL32AXF encoding comes from microMIPS32
and microMIPS32 DSP. Add comment here to help reading.
Please review, thanks.
Regards,
chenwj
Signed-off-by: Chen Wei-Ren
---
target-mips/translate.c | 17 +
1 files changed, 17 insertions(+), 0 deletion
2.34.pdf
Thanks, Eric. I would like to add a comment here to remind
me where they come. :)
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
Hi all,
I check MIPS microMIPS manual [1], and found the major opcode might be
wrong. I add a comment to explicitly indicate what manual I am refering
to, and according that manual I remove microMIPS32 major opcodes 0x1f.
As for others, like 0x16, 0x17, 0x36 and 0x37, they are for higher-order
M
Volume II-B:
The microMIPS32 Instruction Set
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
Do not change the names. The LD32 and SD32 are microMIPS specific. The
> assembler LD and SD opcodes work for either MIPS64 or microMIPS64.
O.K., thanks for the help. :)
How about DADDIU32, should I keep the 32 suffix, too?
I still can't find where POOL32S is.
Regards,
chenwj
--
We
ke to point it out?
Thanks.
Regards,
chenwj
[1] MIPS Architecture For Programmers
Volume I-B: Introduction to the microMIPS64 Architecture
MD00743-2B-microMIPS64INT-AFP-03.02.pdf
[2] MIPS Architecture For Programmers
Volume II-A: The MIPS64 Instruction Set
MD00087-2B-MIPS64BIS-
Hi all,
I check MIPS microMIPS manual [1], and found the major opcode might be
wrong. I add a comment to explicitly indicate what manual I am refering
to, and according that manual I remove some microMIPS32 major opcodes.
Major opcode 0x1f is reserved, so I just remove it. As for others, like
0x
too large!\n");
^^^
wrong ident?
> +if (*end) {
> error_report("Invalid image size specified! You may use k, M, G
> or "
>"T suffixes for ");
> error_report("kilobytes, megabytes, gigabytes and
uint8_t **data,
> + target_phys_addr_t *loadaddr)
^^
Use hwaddr instead. I guess you need rebase to the trunk which
replace target_phys_addr_t with hwaddr everywhere.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Instit
ageBlob {
> +char *name;
> +target_phys_addr_t addr;
ditto.
Regards,
chenwj
[1]
http://git.qemu.org/qemu.git/commit/?id=51ef67270b1d10e1fcf3de7368dccad1ba0bf9d1
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886
o send your patchset. By deafult, `git send-mail`
should thread your patch together, which means every patch in the series
will be threaded to reply the first (cover) letter.
Regards,
chenwj
[1] http://wiki.qemu.org/Contribute/SubmitAPatch
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute
slow-down of kernel boot after this set was applied.
Would you like to try to run some benchmark after the kernel booting? Like
Yeongkyoon Lee done with his qemu_ld/qemu_st work [1], EEMBC, nbench
, or even SPEC. ;)
Regards,
chenwj
[1] http://lists.gnu.org/archive/html/qemu-devel/2012-10/ms
On Wed, Oct 24, 2012 at 12:11:23PM +0900, Yeongkyoon Lee wrote:
> On 2012년 10월 24일 00:25, 陳韋任 (Wei-Ren Chen) wrote:
> > Hi Yeongkyoon,
> >
> >> +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
> >> +/* check whether the give ad
Hi Yeongkyoon,
> +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
> +/* check whether the give addr is in TCG generated code buffer or not */
should be given.
Cheers,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab
(much like qemu), but VirtualBox worked surprisingly well and uses the
> CPU natively (no emulation, faster than my qemu without kvm).
IIRC, VirtualBox take approach similar to kqemu does, i.e.,
translate privilege instructions only and run non-privilege
instructions on host cpu directl
wiki page so that people who want to be a
maintainer know what they should do. :)
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
> I would like to still submit our patches .
>
> Please advise.
>
> Out port is complete and already tested to a level which would be
> difficult for someone else to do that does not have access to our AVP
> test suite.
What about Jia's patch?
Regards,
che
]
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
ach is a minor patch which fix a typo (I guess).
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
diff --git a/docs/instrumentation.txt b/docs/instrumentation.
it.
>
> You can get some instructions here:
>
> https://projects.gso.ac.upc.edu/projects/qemu-dbi/wiki
The website is down. :/ Would you like to take a look on that?
Thanks.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia S
r. Would you interest in contributing
this part?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
> Excuse me for asking, does TCG-IR use static single assignment (SSA) form?
>
> I just wanna know how to translate a register-based bytecode to TCG-IR.
Sounds like you need to take a look at target-xxx/translate.c ?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Ins
hive/html/qemu-devel/2012-09/msg00379.html
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
you confirm this? I am not sure how complete AMD SVM support
in QEMU. :)
Regards,
chenwj
[1] http://wiki.qemu.org/ChangeLog/old
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: h
012-08/msg05037.html
I also think multithread support in qemu user mode is buggy, not only
the issue mentioned on above thread.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
#hellogcc on freenode
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
> My final goal is to obtain the memory access trace for a particular
> process in the guest, so your patch really helps, except for too many
> kernel _mmu events.
How do you know guest is running which process, and log it's memory
access trace?
Regards,
chenwj
--
Wei
On Sat, Aug 25, 2012 at 08:50:29AM -0700, Michael Eager wrote:
> On 08/25/2012 08:38 AM, 陳韋任 (Wei-Ren Chen) wrote:
> >> I want to add a new guest architecture.
> >>
> >> Is there any description of what the configuration options mean?
> >
> >Y
On Sat, Aug 25, 2012 at 08:33:41AM -0700, Michael Eager wrote:
> On 08/25/2012 05:57 AM, 陳韋任 (Wei-Ren Chen) wrote:
> > On Fri, Aug 24, 2012 at 05:46:43PM -0700, Michael Eager wrote:
> >> Is there a description of how to add a new processor architecture
> >> to QEMU?
> I want to add a new guest architecture.
>
> Is there any description of what the configuration options mean?
You mean the options list in `../${QEMU_SRC}/configure --help`?
Not sure why you need to care about that.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Ins
On Sat, Aug 25, 2012 at 11:56:13AM +0100, Peter Maydell wrote:
> On 24 August 2012 04:14, 陳韋任 (Wei-Ren Chen) wrote:
> > I would like to know if there is a function in QEMU which converts
> > a guest physical address into corresponding host virtual address.
>
> So the que
dd a new guest,
tcg/xxx/ if you want to add a new host.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
r;
... snip ...
}
Regards,
chenwj
[1]
http://download.intel.com/products/processor/manual/253668.pdf
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
t;
> It may be we're deliberately (mis)using target_ulong to get the
> right behaviour on both 32 and 64 bit cores.
Need to be further investigated. :)
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
anything.
True, the inline tlb lookup will take some space on icache, but I
believe it's not a big deal since you're on a x86 host.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
e performance degradation. If software
tlb hit, you can get the value of guest memory in the code cache
with a few host instructions. Disabling software tlb lookup, every guest
memory access will call a helper function which takes a lot of time.
What you mean by "get rid of that piece of genera
ss. IIUC, pde_addr and pte_addr should be the
guest physical address for guest page table and guest page respectively,
right? If no one object, I'll send a patch which replaces target_ulong
with target_phys_addr_t.
Thanks.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Instit
tion "cpu_physical_memory_unmap", the comment
of it says,
Unmaps a memory region previously mapped by cpu_physical_memory_map().
That makes me not sure if I use cpu_physical_memory_map correctly,
does it do what I want to do?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Comput
virtual address into a file or
something else, then insert a helper function call at the point of
TLB hit.
HTH,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
s,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
On Wed, Aug 22, 2012 at 09:38:17PM -0700, Xin Tong wrote:
> On Wed, Aug 22, 2012 at 8:14 PM, 陳韋任 (Wei-Ren Chen)
> wrote:
> >> In tcg_gen_qemu_ld8s(tmp, addr, index); a TCGv addr is passed to the
> >> INDEX_op_qemu_ld8s as param and the loaded value is passed back in
>
= (env->cr[3] + 32 * 4) & env->a20_mask;
target_phys_addr_t len = 4;
void *ptr = cpu_physical_memory_map(pde_addr, &len, 0);
The only thing I am not sure about is what value of len I should use.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of
e in that address into tmp. So, what "translated value" you mean
here? The guest physical address, host virtual address, or the value
of the guest virtual address?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O
, which works fine now.
Another question is, I would like to know the hva corresponding to gpa (i.e.,
the guest page pointed by guest pte). Do you happen to know there is such
gpa2hva function in QEMU?
Thanks.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of
directly.
^^^
Would be better if you make it align.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
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