Re: [PATCH] target/riscv: Stop timer with infinite timecmp

30.08.2024 17:50, Andrew Jones пишет: > On Fri, Aug 30, 2024 at 02:05:05PM GMT, Vladimir Isaev wrote: >> Hi Andrew, >> >> 29.08.2024 11:40, Andrew Jones wrote: >>> While the spec doesn't state it, setting timecmp to UINT64_MAX is >>> another way to

Re: [PATCH] target/riscv: Stop timer with infinite timecmp

since some software may initially set time and timecmp to big values just to check how overflow is handled. And without it no chance that all HW implementations will interpret UINT64_MAX as 'stop timer'. Do we need github issue on SSTC/privileged? Thank you, Vladimir Isaev >

[PATCH] target/riscv: fix za64rs enabling

t;) Signed-off-by: Vladimir Isaev --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a90808a3bace..07a7af59b6d9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,7 +115,7 @@ const RISCVIsaExtData isa

Re: [PATCH v4 00/17] target/riscv: deprecate riscv_cpu_options[]

v/20240103174013.147279-1-dbarb...@ventanamicro.com/ > > This series work fine in my tests as well, thank you! (sorry for the delay) TCG part: Tested-by: Vladimir Isaev > Daniel Henrique Barboza (17): > target/riscv/cpu_cfg.h: remove unused fields > target/riscv: make ris

Re: [PATCH v2 00/16] target/riscv: deprecate riscv_cpu_options[]

> > target/riscv/cpu.c | 584 +-- > target/riscv/cpu.h | 7 +- > target/riscv/cpu_cfg.h | 4 - > target/riscv/kvm/kvm-cpu.c | 94 +++--- > target/riscv/kvm/kvm_riscv.h | 1 + > target/riscv/tcg/tcg-cpu.c | 63 > 6 files changed, 561 insertions(+), 192 deletions(-) > > -- > 2.43.0 > > For whole series and TCG part: Tested-by: Vladimir Isaev

Re: [PATCH v2 10/16] target/riscv: create finalize_features() for KVM

22.12.2023 15:22, Daniel Henrique Barboza wrote: > To turn cbom_blocksize and cboz_blocksize into class properties we need > KVM specific changes. > > KVM is creating its own version of these options with a customized > setter() that prevents users from picking an invalid value during init() > tim

Re: [PATCH v2 08/16] target/riscv: move 'vlen' to riscv_cpu_properties[]

22.12.2023 15:22, Daniel Henrique Barboza wrote: > > Turning 'vlen' into a class property will allow its default value to be > overwritten by cpu_init() later on, solving the issue we have now where > CPU specific settings are getting overwritten by the default. > > For 'vlen', 'elen' and the blo

Re: [PATCH v2 01/16] target/riscv/cpu_cfg.h: remove user_spec and bext_spec

22.12.2023 15:22, Daniel Henrique Barboza wrote:> > They aren't being used. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu_cfg.h | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index f4605fb190..c67a8731d3 100644

Re: [PATCH] target/riscv/tcg: do not set defaults for non-generic

29.12.2023 12:15, Daniel Henrique Barboza wrote: > > On 12/29/23 05:02, Vladimir Isaev wrote: >> riscv_cpu_options[] are exported using qdev and some of them are defined >> with default values. This is unfortunate since >> riscv_cpu_add_user_properties() >> is call

[PATCH] target/riscv/tcg: do not set defaults for non-generic

need defaults for generic CPU. Signed-off-by: Vladimir Isaev --- target/riscv/tcg/tcg-cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a345d..9ffce1c9f7b0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/risc

Re: [PATCH] target/riscv: pmp: Clear pmp/smepmp bits on reset

um = pmp_get_num_rules(env); > +int i; > + > +for (i = 0; i < pmp_num; i++) { > +env->pmp_state.pmp[i].cfg_reg &= ~PMP_LOCK; According to spec: Writable PMP registers’ A and L fields are set to 0, unless the platform mandates a different reset value for s

[PATCH v2] target/riscv: fix ctzw behavior

According to spec, ctzw should work with 32-bit register, not 64. For example, previous implementation returns 33 for (1<<33) input when the new one returns 32. Signed-off-by: Vladimir Isaev Suggested-by: Richard Henderson --- v2: - Use simpler solution suggested by Richard Hen

[PATCH] target/riscv: fix SBI getchar handler for KVM

Character must be returned via ret[0] field (copied to a0 by KVM). Return value should be set to 0 to indicate successful processing. Signed-off-by: Vladimir Isaev --- target/riscv/kvm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/kvm.c b/target/riscv

[PATCH] target/riscv: fix ctzw behavior

According to spec, ctzw should work with 32-bit register, not 64. For example, previous implementation returns 33 for (1<<33) input when the new one returns 32. Signed-off-by: Vladimir Isaev --- target/riscv/insn_trans/trans_rvb.c.inc | 9 - 1 file changed, 8 insertions(+), 1 de