[PATCH] hw/char: Add config for shakti uart

Use a dedicated UART config(CONFIG_SHAKTI_UART) to select shakti uart. Signed-off-by: Vijai Kumar K --- hw/char/Kconfig | 3 +++ hw/char/meson.build | 2 +- hw/riscv/Kconfig| 5 + 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/char/Kconfig b/hw/char/Kconfig index

[PATCH] docs: Add documentation for shakti_c machine

Add documentation for Shakti C reference platform. Signed-off-by: Vijai Kumar K --- docs/system/riscv/shakti-c.rst | 82 ++ 1 file changed, 82 insertions(+) create mode 100644 docs/system/riscv/shakti-c.rst diff --git a/docs/system/riscv/shakti-c.rst b/docs

Re: [PATCH v3 0/4] Add support for Shakti SoC from IIT-M

On Sat, 03 Apr 2021 01:35:25 +0530 Alistair Francis wrote > On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote: > > > > Changes in v3: > > - Drop SHAKTI_C_DEBUG register > > > > Changes in v2: > > - Moved CPU additi

Re: [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform

On Fri, 02 Apr 2021 18:35:04 +0530 Alistair Francis wrote > On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote: > > > > Connect one shakti uart to the shakti_c machine. > > > > Signed-off-by: Vijai Kumar K > > In future can you plea

[PATCH v3 0/4] Add support for Shakti SoC from IIT-M

shakti - Error out when an unsupported CPU is specified - Addressed formatting changes pointed out in review Vijai Kumar K (4): target/riscv: Add Shakti C class CPU riscv: Add initial support for Shakti C machine hw/char: Add Shakti UART emulation hw/riscv: Connect Shakti UART to Shakti

[PATCH v3 3/4] hw/char: Add Shakti UART emulation

This is the initial implementation of Shakti UART. Signed-off-by: Vijai Kumar K --- MAINTAINERS | 2 + hw/char/meson.build | 1 + hw/char/shakti_uart.c | 185 ++ hw/char/trace-events | 4 + include/hw/char

[PATCH v3 2/4] riscv: Add initial support for Shakti C machine

Add support for emulating Shakti reference platform based on C-class running on arty-100T board. https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst Signed-off-by: Vijai Kumar K --- MAINTAINERS | 7 + default-configs/devices/riscv64

[PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform

Connect one shakti uart to the shakti_c machine. Signed-off-by: Vijai Kumar K --- hw/riscv/shakti_c.c | 8 include/hw/riscv/shakti_c.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index c8205d3f22..e207fa83dd 100644 --- a/hw

[PATCH v3 1/4] target/riscv: Add Shakti C class CPU

C-Class is a member of the SHAKTI family of processors from IIT-M. It is an extremely configurable and commercial-grade 5-stage in-order core supporting the standard RV64GCSUN ISA extensions. Signed-off-by: Vijai Kumar K --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 2 files changed

Re: [PATCH v2 2/4] riscv: Add initial support for Shakti C machine

On Thu, 01 Apr 2021 22:51:42 +0530 Alistair Francis wrote > On Thu, Apr 1, 2021 at 1:18 PM Vijai Kumar K wrote: > > > > > > > > > > On Wed, 31 Mar 2021 21:05:47 +0530 Alistair Francis > > wrote > > > &g

Re: [PATCH v2 2/4] riscv: Add initial support for Shakti C machine

On Wed, 31 Mar 2021 21:05:47 +0530 Alistair Francis wrote > On Sun, Mar 21, 2021 at 1:09 AM Vijai Kumar K wrote: > > > > Add support for emulating Shakti reference platform based on C-class > > running on arty-100T board. > > > > https

[PATCH v2 2/4] riscv: Add initial support for Shakti C machine

Add support for emulating Shakti reference platform based on C-class running on arty-100T board. https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst Signed-off-by: Vijai Kumar K --- MAINTAINERS | 7 + default-configs/devices/riscv64

[PATCH v2 3/4] hw/char: Add Shakti UART emulation

This is the initial implementation of Shakti UART. Signed-off-by: Vijai Kumar K --- MAINTAINERS | 2 + hw/char/meson.build | 1 + hw/char/shakti_uart.c | 185 ++ hw/char/trace-events | 4 + include/hw/char

[PATCH v2 0/4] Add support for Shakti SoC from IIT-M

sifive_u_cpu_init routine for shakti - Error out when an unsupported CPU is specified - Addressed formatting changes pointed out in review Vijai Kumar K (4): target/riscv: Add Shakti C class CPU riscv: Add initial support for Shakti C machine hw/char: Add Shakti UART emulation hw/riscv: Connect

[PATCH v2 4/4] hw/riscv: Connect Shakti UART to Shakti platform

Connect one shakti uart to the shakti_c machine. Signed-off-by: Vijai Kumar K --- hw/riscv/shakti_c.c | 8 include/hw/riscv/shakti_c.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 45d0eedabd..6174136ffa 100644 --- a/hw

[PATCH v2 1/4] target/riscv: Add Shakti C class CPU

C-Class is a member of the SHAKTI family of processors from IIT-M. It is an extremely configurable and commercial-grade 5-stage in-order core supporting the standard RV64GCSUN ISA extensions. Signed-off-by: Vijai Kumar K --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 2 files changed

Re: [PATCH 1/3] riscv: Add initial support for Shakti C class

On Fri, 19 Mar 2021 19:09:17 +0530 Alistair Francis wrote > On Sun, Mar 14, 2021 at 5:10 AM Vijai Kumar K wrote: > > > > C-Class is a member of the SHAKTI family of processors from Indian > > Institute of Technology - Madras(IIT-M). > > It i

Re: [PATCH 2/3] hw/char: Add Shakti UART emulation

On Fri, 19 Mar 2021 19:14:31 +0530 Alistair Francis wrote > On Sun, Mar 14, 2021 at 5:14 AM Vijai Kumar K wrote: > > > > This is the initial implementation of Shakti UART. > > > > TX tested and works fine. RX is untested. > >

[PATCH] hw/riscv: Drop the unused fdt pointer

Drop the unused fdt pointer in riscv_setup_rom_reset_vec API. Signed-off-by: Vijai Kumar K --- hw/riscv/boot.c | 2 +- hw/riscv/spike.c| 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv

Re: [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform

On Fri, 19 Mar 2021 19:17:58 +0530 Alistair Francis wrote > On Sun, Mar 14, 2021 at 5:11 AM Vijai Kumar K wrote: > > > > Connect one shakti uart to the shakti_c machine. > > > > Signed-off-by: Vijai Kumar K > > --- >

[PATCH 2/3] hw/char: Add Shakti UART emulation

This is the initial implementation of Shakti UART. TX tested and works fine. RX is untested. Signed-off-by: Vijai Kumar K --- MAINTAINERS | 2 + hw/char/meson.build | 1 + hw/char/shakti_uart.c | 204 ++ hw/char/trace

[PATCH 1/3] riscv: Add initial support for Shakti C class

arty-100T platform. https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst Signed-off-by: Vijai Kumar K --- MAINTAINERS | 7 + default-configs/devices/riscv64-softmmu.mak | 1 + hw/riscv/Kconfig| 10 ++ hw

[PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform

Connect one shakti uart to the shakti_c machine. Signed-off-by: Vijai Kumar K --- hw/riscv/shakti_c.c | 7 +++ include/hw/riscv/shakti_c.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index e96436a3bf..07cc42a380 100644 --- a/hw

[PATCH 0/3] Add support for Shakti SoC from IIT-M

[3] https://gitlab.com/shaktiproject/uncore/devices/-/tree/master/uart_v2 Vijai Kumar K (3): riscv: Add initial support for Shakti C class hw/char: Add Shakti UART emulation hw/riscv: Connect Shakti UART to Shakti platform MAINTAINERS | 9 + default-configs