On 11.08.2016 00:42, David Kiarie wrote:
Report IOAPIC via IVRS which effectively allows linux AMD-Vi
driver to enable interrupt remapping
Signed-off-by: David Kiarie
---
hw/i386/acpi-build.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
inde
On 11.08.2016 00:42, David Kiarie wrote:
Introduce AMD IOMMU interrupt remapping and hook it onto
the existing interrupt remapping infrastructure
Signed-off-by: David Kiarie
---
hw/i386/amd_iommu.c | 226 +++-
hw/i386/amd_iommu.h | 2 +
2 files
On 13.08.2016 00:40, David Kiarie wrote:
On Fri, Aug 12, 2016 at 10:10 PM, Valentine Sinitsyn
mailto:valentine.sinit...@gmail.com>> wrote:
Hi David,
On 02.08.2016 13:39, David Kiarie wrote:
Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU.
The IOMM
On 11.08.2016 00:42, David Kiarie wrote:
Introduce macros and trace events for use in AMD IOMMU
interrupt remapping
Signed-off-by: David Kiarie
---
hw/i386/amd_iommu.h | 72
hw/i386/trace-events | 7 +
2 files changed, 79 insertions(+)
Hi David,
On 02.08.2016 13:39, David Kiarie wrote:
Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU.
The IOMMU does basic translation, error checking and has a
minimal IOTLB implementation. This IOMMU bypassed the need
for target aborts by responding with IOMMU_NONE access rights
and ex
On 11.08.2016 13:32, David Kiarie wrote:
On Thu, Aug 11, 2016 at 11:23 AM, Valentine Sinitsyn
mailto:valentine.sinit...@gmail.com>> wrote:
Hi,
On 02.08.2016 13:39, David Kiarie wrote:
+static void amdvi_writeq_raw(AMDVIState *s, uint64_t val,
hwadd
Hi,
On 02.08.2016 13:39, David Kiarie wrote:
Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU.
The IOMMU does basic translation, error checking and has a
minimal IOTLB implementation. This IOMMU bypassed the need
for target aborts by responding with IOMMU_NONE access rights
and exempts
Hi David,
On 11.08.2016 00:42, David Kiarie wrote:
Hello all,
The following patchset adds AMD-Vi interrupt remapping logic
to Qemu and hooks it onto existing interrupt remapping infrastructure.It has
a dependency on "Explicit SID for IOAPIC" patchset though.
I would appreciate your feedback!
On 09.08.2016 19:32, David Kiarie wrote:
Platform device are now able to make interrupt request with
explicit SIDs hence we can safely expect triggered AddressSpace ID
to match the requesting ID
Signed-off-by: David Kiarie
---
hw/i386/intel_iommu.c | 82 +++---
Hi all,
On 09.08.2016 17:52, David Kiarie wrote:
On Tue, Aug 9, 2016 at 8:44 AM, Peter Xu mailto:pet...@redhat.com>> wrote:
On Tue, Aug 02, 2016 at 11:39:06AM +0300, David Kiarie wrote:
[...]
> +/* invalidate internal caches for devid */
> +typedef struct QEMU_PACKED {
>
Hi all,
On 24.05.2016 11:54, Peter Xu wrote:
On Sun, May 22, 2016 at 01:21:52PM +0300, David Kiarie wrote:
[...]
+static void
+build_amd_iommu(GArray *table_data, GArray *linker)
+{
+int iommu_start = table_data->len;
+bool iommu_ambig;
+
+/* IVRS definition - table header has an e
On 04.05.2016 16:02, David Kiarie wrote:
On 04/05/16 13:58, Valentine Sinitsyn wrote:
On 04.05.2016 15:51, David Kiarie wrote:
On Wed, May 4, 2016 at 10:39 AM, Valentine Sinitsyn
wrote:
Hi everyone,
On 04.05.2016 12:05, David Kiarie wrote:
On Wed, May 4, 2016 at 9:12 AM, Jan Kiszka
On 04.05.2016 15:51, David Kiarie wrote:
On Wed, May 4, 2016 at 10:39 AM, Valentine Sinitsyn
wrote:
Hi everyone,
On 04.05.2016 12:05, David Kiarie wrote:
On Wed, May 4, 2016 at 9:12 AM, Jan Kiszka wrote:
On 2016-04-30 00:42, David Kiarie wrote:
These series adds AMD IOMMU support to
On 29.04.2016 13:28, David Kiarie wrote:
On Fri, Apr 29, 2016 at 9:09 AM, Jan Kiszka wrote:
On 2016-04-25 00:12, David Kiarie wrote:
Add IVRS table for AMD IOMMU. Generate IVRS or DMAR
depending on emulated IOMMU
It seems you lack scope descriptions for the PCI devices in the system.
At le
On 29.04.2016 11:09, Jan Kiszka wrote:
On 2016-04-25 00:12, David Kiarie wrote:
Add IVRS table for AMD IOMMU. Generate IVRS or DMAR
depending on emulated IOMMU
It seems you lack scope descriptions for the PCI devices in the system.
At least, this is what our jailhouse config generator complain
Hi everyone,
On 04.05.2016 12:05, David Kiarie wrote:
On Wed, May 4, 2016 at 9:12 AM, Jan Kiszka wrote:
On 2016-04-30 00:42, David Kiarie wrote:
These series adds AMD IOMMU support to Qemu. It's currently in the 9th version.
In this series I have (hopefully) addressed all the comments made i
Hi all,
I recall I saw IVRS filling code in the coreboot for one of the boards
supported. David, you may want to have a look there.
Valentine
(from the phone)
On Jan 14, 2016 9:29 PM, "Kevin O'Connor" wrote:
> On Thu, Jan 14, 2016 at 12:09:46PM +0200, Michael S. Tsirkin wrote:
> > On Thu, Jan 1
e current Qemu
infrastructure - Qemu doesn't implement anything that's related to PASID.
Similary, guest translation won't be possible.
Note: I have not tested this code and it might have a few bugs (silly bugs) of
course but the RFC version works so, if present, it's just minor bugs.
Regards,
Valentine Sinitsyn
On 09.10.2015 17:22, David kiarie wrote:
On Fri, Oct 9, 2015 at 10:17 AM, Valentine Sinitsyn
wrote:
Hi David,
Thanks for your efforts.
On 09.10.2015 07:53, David Kiarie wrote:
David (4):
hw/core: Add iommu to machine properties
hw/pci-host: Add AMD IOMMU to PIIX and Q35 pcs
hw
On 09.10.2015 17:27, David kiarie wrote:
On Fri, Oct 9, 2015 at 3:24 PM, Valentine Sinitsyn
wrote:
On 09.10.2015 17:22, David kiarie wrote:
On Fri, Oct 9, 2015 at 10:17 AM, Valentine Sinitsyn
wrote:
Hi David,
Thanks for your efforts.
On 09.10.2015 07:53, David Kiarie wrote:
David (4
Hi David,
On 07.09.2015 17:46, Valentine Sinitsyn wrote:
...snip...
+/* TODO : Mark addresses as Accessed and Dirty */
+static void amd_iommu_do_translate(AMDIOMMUAddressSpace *as, hwaddr
addr, bool is_write, IOMMUTLBEntry *ret)
+{
+AMDIOMMUState *s = as->iommu_state;
+
+int pres
Oops, that was a long ago. Sorry & thanks.
Valentine
On 09.09.2015 13:12, David kiarie wrote:
I wrote something basic on the cover letter
http://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg02759.html
On Wed, Sep 9, 2015 at 11:07 AM, Valentine Sinitsyn
wrote:
On 09.09.2015 1
On 09.09.2015 12:59, David kiarie wrote:
On Wed, Sep 9, 2015 at 10:45 AM, Valentine Sinitsyn
wrote:
On 09.09.2015 12:30, David kiarie wrote:
...snip...
+static void amd_iommu_cmdbuf_exec(AMDIOMMUState *s)
+{
+unsigned type;
+uint8_t cmd[IOMMU_COMMAND_SIZE];
+
+IOMMU_DPRINTF
On 09.09.2015 12:59, Michael S. Tsirkin wrote:
On Wed, Sep 09, 2015 at 12:45:10PM +0500, Valentine Sinitsyn wrote:
On 09.09.2015 12:30, David kiarie wrote:
...snip...
+static void amd_iommu_cmdbuf_exec(AMDIOMMUState *s)
+{
+unsigned type;
+uint8_t cmd[IOMMU_COMMAND_SIZE
On 09.09.2015 12:30, David kiarie wrote:
...snip...
+static void amd_iommu_cmdbuf_exec(AMDIOMMUState *s)
+{
+unsigned type;
+uint8_t cmd[IOMMU_COMMAND_SIZE];
+
+IOMMU_DPRINTF(COMMAND, "");
+memset(cmd, 0, IOMMU_COMMAND_SIZE);
+
+if(dma_memory_read(&address_space_memory, s->cm
On 09.09.2015 11:54, David kiarie wrote:
...snip...
Most recent work is here
http://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg02759.html
. Most the code is Qemu device boilerplate(so there are a ton of
things to add but I wanted to have the existing work merged first).
The IOMMU just of
Hi all,
On 09.09.2015 09:23, David kiarie wrote:
On Wed, Sep 9, 2015 at 12:35 AM, Jan Kiszka wrote:
[thanks for forwarding, Peter]
Hi Rita,
On 2015-09-08 10:11, Peter Maydell wrote:
On 7 September 2015 at 22:31, Rita Sinha wrote:
Hi Jan,
I am interested in participating in next round of
Hi David,
Sorry for the long silence. I've skimmed through your patch, below are
some thoughts. Please remember I'm looking for IOMMU implementation
details, not how it is integrated with QEMU.
On 25.08.2015 04:19, David Kiarie wrote:
From: David
Add AMD IOMMU emulation to Qemu. This is a
Hi,
On 25.08.2015 04:19, David Kiarie wrote:
From: David
Add AMD IOMMU emulation to Qemu. This is a very basic AMD IOMMU
emulation that only does translation and some basic Event logging.
Guest translation enables nested PCI passthrough
Signed-off-by: David Kiarie
---
hw/i386/Makefile.objs
On 25.08.2015 12:41, David kiarie wrote:
On Tue, Aug 25, 2015 at 10:31 AM, Valentine Sinitsyn
[...snip...]
The spec doesn't say anything about this, I checked it. IIRC, I came across
this behavior when submitted COMPLETION_WAIT command with interrupts off and
spin in a while() loop waitin
On 25.08.2015 12:25, David kiarie wrote:
On Tue, Aug 25, 2015 at 9:39 AM, Valentine Sinitsyn
wrote:
Hi,
On 25.08.2015 04:19, David Kiarie wrote:
From: David
Add AMD IOMMU emulation to Qemu. This is a very basic AMD IOMMU
emulation that only does translation and some basic Event logging
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