Re: [RFC] target/arm: Concerns about mixed endian support for remote GDB

ell wrote: > On Fri, 18 Jul 2025 at 20:20, Vacha Bhavsar > wrote: > > > > Upon examining the current implementation for getting/setting SIMD > > and SVE registers via remote GDB, there is a concern about mixed > > endian support. > > Yes, we discussed this on a diff

[PATCH 1/2] target/arm: Fix big-endian handling of NEON gdb remote debugging

endianness to ensure the most significant bits are always in second element. Signed-off-by: Vacha Bhavsar --- target/arm/gdbstub64.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 64ee9b3b56..8b7f15b920 100644 --- a

[PATCH 0/2] target/arm: Fix big-endian handling for NEON and SVE gdb remote debugging

or NEON registers, and the second patch will do so for SVE registers. Vacha Bhavsar (2): This patch adds big endian support for NEON GDB remote debugging. It replaces the use of ldq_le_p() with the use of ldq_p() as explained in the first part of this patch series. Additionally, the order

[PATCH 2/2] target/arm: Fix big-endian handling of SVE gdb remote debugging

target endianness to ensure the most significant bits are always in second element. Signed-off-by: Vacha Bhavsar --- target/arm/gdbstub64.c | 18 +- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 8b7f15b920

[RFC] target/arm: Concerns about mixed endian support for remote GDB

Upon examining the current implementation for getting/setting SIMD and SVE registers via remote GDB, there is a concern about mixed endian support. Consider the following snippet from a GDB session in which a SIMD register's value is set via remote GDB where the QEMU host is little endian and the

Re: [PATCH v2] target/arm: Added support for SME register exposure to GDB

Hi Richard, Thank you for the feedback! I have sent an updated version your way with the suggested changes! Thanks, Vacha On Mon, Jul 14, 2025 at 3:41 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/14/25 11:43, Vacha Bhavsar wrote: > > diff --git a/target/ar

[PATCH v3] target/arm: Added support for SME register exposure to GDB

dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Signed-off-by: Vacha Bhavsar --- Changes since v2: - Used FIELD_EX64(env->svcr, SVCR, SM) to determine streaming mode to set value of vq in aarch64_gdb_get_sme_reg() - Changed occurrences of sve_max

Re: [PATCH] target/arm: Added support for SME register exposure to GDB

, 2025 at 6:30 AM Peter Maydell wrote: > On Tue, 8 Jul 2025 at 23:14, Vacha Bhavsar > wrote: > > > > The QEMU GDB stub does not expose the ZA storage SME register to GDB via > > the remote serial protocol, which can be a useful functionality to debug > SME > > code. To

[PATCH v2] target/arm: Added support for SME register exposure to GDB

dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Signed-off-by: Vacha Bhavsar --- Changes since v1: - Removed unnecessary comments in aarch64_gdb_set_sme_reg() regarding the zregs - Used aarch64_set_svcr to correctly set the 64 bit SVCR in

Re: [PATCH] target/arm: Added support for SME register exposure to GDB

it to the next release. Thanks, Vacha On Tue, Jul 8, 2025 at 6:14 PM Vacha Bhavsar wrote: > The QEMU GDB stub does not expose the ZA storage SME register to GDB via > the remote serial protocol, which can be a useful functionality to debug > SME > code. To provide this functional

[PATCH] target/arm: Added support for SME register exposure to GDB

dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Signed-off-by: Vacha Bhavsar --- target/arm/cpu.h | 1 + target/arm/gdbstub.c | 6 +++ target/arm/gdbstub64.c | 119 + target/arm/internals.h | 3