Re: [PATCH] target/ppc: Fix regression in Radix MMU

ising exceptions. Fixes: 47e83d9107 ("target/ppc: Improve Radix xlate level validation") Reported-by: Victor Colombo Signed-off-by: Leandro Lupori It now reaches the login screen on L2 Tested-by: Víctor Colombo -- Víctor Cora Colombo Instituto de Pesquisas ELDORADO Aviso Legal - Di

[RFC PATCH v2 5/5] target/ppc: Enable hardfpu for Power

Change the build conditional from softfloat.c, allowing TARGET_PPC to use hardfpu. For PPC, this is only implemented in linux-user. Signed-off-by: Víctor Colombo --- fpu/softfloat.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c

[RFC PATCH v2 1/5] target/ppc: prepare instructions to work with caching last FP insn

o. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 6 +++ target/ppc/excp_helper.c | 2 + target/ppc/fpu_helper.c| 71 ++ target/ppc/helper.h| 1 + target/ppc/translate/fp-impl.c.inc | 1 + 5 files c

[RFC PATCH v2 3/5] target/ppc: Implement instruction caching for muladd

updating the relevant flags, as is today. This implementation only works in linux-user. No test or effort was done in this patch to make it work for softmmu. Future work will be required to make it work correctly in this scenario. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h| 11

[RFC PATCH v2 4/5] target/ppc: Implement instruction caching for add/sub/mul/div

updating the relevant flags, as is today. This implementation only works in linux-user. No test or effort was done in this patch to make it work for softmmu. Future work will be required to make it work correctly in this scenario. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h| 9

[RFC PATCH v2 2/5] target/ppc: Implement instruction caching for fsqrt

-off-by: Víctor Colombo --- target/ppc/cpu.h| 11 +++ target/ppc/fpu_helper.c | 40 +++- 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 116ee639ff..e55c10b0db 100644 --- a/target/ppc/cpu.h

[RFC PATCH v2 0/5] Idea for using hardfloat in PPC

/patch/20200218171702.979f0746...@zero.eik.bme.hu/ [4] https://gist.github.com/vcoracolombo/6ad884a402f1bba531e2e3da7e196656 [5] https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg00064.html [6] https://gist.github.com/vcoracolombo/f0d8b7c9f1cb63dac6ff0221209ec4ff [7] https://gist.github.com/vcor

[RFC PATCH 2/4] target/ppc: Implement instruction caching for fsqrt

float_flag_inexact cleared, forcing softfloat and correctly updating the relevant flags, as is today. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h| 11 +++ target/ppc/fpu_helper.c | 39 ++- 2 files changed, 49 insertions(+), 1 deletion

[RFC PATCH 0/4] Idea for using hardfloat in PPC

...@zero.eik.bme.hu/ [4] https://gist.github.com/vcoracolombo/6ad884a402f1bba531e2e3da7e196656 [5] https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg00064.html Víctor Colombo (4): target/ppc: prepare instructions to work with caching last FP insn target/ppc: Implement instruction

[RFC PATCH 3/4] target/ppc: Implement instruction caching for muladd

updating the relevant flags, as is today. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h| 11 +++ target/ppc/fpu_helper.c | 34 -- 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b423e33a0c

[RFC PATCH 4/4] target/ppc: Enable hardfpu for Power

Remove the build conditional from softfloat.c, allowing TARGET_PPC to use hardfpu. Signed-off-by: Víctor Colombo --- fpu/softfloat.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c7454c3eb1..de94732f6a 100644 --- a/fpu

[RFC PATCH 1/4] target/ppc: prepare instructions to work with caching last FP insn

future, it will be necessary to implement the necessary code for each FP instruction that wants to use hardfpu. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 6 +++ target/ppc/excp_helper.c | 2 + target/ppc/fpu_helper.c

[PATCH] target/ppc: Fix xvcmp* clearing FI bit

) Signed-off-by: Víctor Colombo --- target/ppc/translate/vsx-impl.c.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 7acdbceec4..e6e5c45ffd 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate

Re: [PATCH 3/3] target/ppc: Merge fsqrt and fsqrts helpers

On 05/09/2022 14:20, Richard Henderson wrote: Well, there would of course be no separate call, but I didn't understand what you meant here with 'no separate call'... do_float_check_status would:     int status = get_float_exception_flags(&env->fp_status);     set_float_exception_flags(0,

[PATCH v2 6/8] target/ppc: Set OV32 when OV is set

According to PowerISA: "OV32 is set whenever OV is implicitly set, and is set to the same value that OV is defined to be set to in 32-bit mode". This patch changes helper_update_ov_legacy to set/clear ov32 when applicable. Signed-off-by: Víctor Colombo Reviewed-by: Daniel Henriq

[PATCH v2 3/8] target/ppc: Zero second doubleword in DFP instructions

p128. This fixes the behavior for ISA 3.1 while keeping the behavior correct for previous ones. Signed-off-by: Víctor Colombo Reviewed-by: Daniel Henrique Barboza --- target/ppc/dfp_helper.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/ppc/dfp_helper.c b/target/

[PATCH v2 2/8] target/ppc: Remove unused xer_* macros

The macros xer_ov, xer_ca, xer_ov32, and xer_ca32 are both unused and hiding the usage of env. Remove them. Signed-off-by: Víctor Colombo Reviewed-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 4 1 file changed, 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index

[PATCH v2 1/8] target/ppc: Remove extra space from s128 field in ppc_vsr_t

Very trivial rogue space removal. There are two spaces between Int128 and s128 in ppc_vsr_t struct, where it should be only one. Signed-off-by: Víctor Colombo Reviewed-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target

[PATCH v2 4/8] target/ppc: Set result to QNaN for DENBCD when VXCVI occurs

bled (VE=0) and Invalid Operation occurs (...) If the operation is an (...) or format the target FPR is set to a Quiet NaN". This was not being done in QEMU. This patch sets the result to QNaN when the instruction DENBCD causes an Invalid Operation Exception. Signed-off-by: Víctor Colombo Reviewed

[PATCH v2 8/8] target/ppc: Clear fpstatus flags on helpers missing it

P_TO_FP_HP - VSX_CVT_FP_TO_FP_VECTOR - VSX_CMP - VSX_ROUND - xscvqpdp - xscvdpsp[n] Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 37 ++--- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_help

[PATCH v2 7/8] target/ppc: Zero second doubleword of VSR registers for FPR insns

: Víctor Colombo Reviewed-by: Daniel Henrique Barboza --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 000b1e518d..5e433315e1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6443,6 +6443,14

[PATCH v2 5/8] target/ppc: Zero second doubleword for VSX madd instructions

("target/ppc: Change VSX instructions behavior to fill with zeros") Signed-off-by: Víctor Colombo Reviewed-by: Daniel Henrique Barboza --- target/ppc/fpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index

[PATCH v2 0/8] Multiple ppc instructions fixes

h merged both reviewed and non-reviewed patches. Now require a new, single R-b. Víctor Colombo (8): target/ppc: Remove extra space from s128 field in ppc_vsr_t target/ppc: Remove unused xer_* macros target/ppc: Zero second doubleword in DFP instructions target/ppc: Set result to

Re: [PATCH 18/19] target/ppc: Clear fpstatus flags on VSX_CMP

On 05/09/2022 15:41, Daniel Henrique Barboza wrote: On 9/1/22 10:17, Víctor Colombo wrote: Signed-off-by: Víctor Colombo --- What I mentioned in patch 10 also applies to all patches from 11 to 18 it seems. All changes made in patches 09-18 are based on the explanation gave in patch 08. The

Re: [PATCH 3/3] target/ppc: Merge fsqrt and fsqrts helpers

On 05/09/2022 13:21, Richard Henderson wrote: On 9/5/22 17:19, Víctor Colombo wrote: Existing bug, but this is missing to clear fp status to start. Reviewed-by: Richard Henderson r~ Hello Richard, thanks for your review! gen_reset_fpstatus() is called by the inline implementation in

Re: [PATCH 3/3] target/ppc: Merge fsqrt and fsqrts helpers

On 05/09/2022 12:56, Richard Henderson wrote: On 9/5/22 13:37, Víctor Colombo wrote: These two helpers are almost identical, differing only by the softfloat operation it calls. Merge them into one using a macro. Also, take this opportunity to capitalize the helper name as we moved the

[PATCH 1/3] target/ppc: Move fsqrt to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 7 +++ target/ppc/translate/fp-impl.c.inc | 29 + target/ppc/translate/fp-ops.c.inc | 1 - 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/target/ppc/insn32.decode b/target

[PATCH 3/3] target/ppc: Merge fsqrt and fsqrts helpers

These two helpers are almost identical, differing only by the softfloat operation it calls. Merge them into one using a macro. Also, take this opportunity to capitalize the helper name as we moved the instruction to decodetree in a previous patch. Signed-off-by: Víctor Colombo --- target/ppc

[PATCH 0/3] target/ppc: Move fsqrt[s] to decodetree

Move fsqrt and fsqrts instructions from decode legacy to decodetree. Víctor Colombo (3): target/ppc: Move fsqrt to decodetree target/ppc: Move fsqrts to decodetree target/ppc: Merge fsqrt and fsqrts helpers target/ppc/fpu_helper.c| 35 - target/ppc/helper.h

[PATCH 2/3] target/ppc: Move fsqrts to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 1 + target/ppc/translate/fp-impl.c.inc | 23 +-- target/ppc/translate/fp-ops.c.inc | 1 - 3 files changed, 2 insertions(+), 23 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32

[PATCH 19/19] target/ppc: Clear fpstatus flags on VSX_ROUND

Fix xsrdpic and other instructions not clearing the flags and saving incorrect values to FPSCR. Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index fd3a966371..be47d73b14 100644

[PATCH 18/19] target/ppc: Clear fpstatus flags on VSX_CMP

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 5f7f52ab5b..fd3a966371 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2639,6 +2639,8 @@ uint32_t helper_

[PATCH 17/19] target/ppc: Clear fpstatus flags for xscvdpsp[n]

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 51142bd7d5..5f7f52ab5b 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2719,6 +2719,8 @@ void helper_

[PATCH 15/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_FP_VECTOR

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 39f0ec7431..627166672c 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2756,6 +2756,8 @@ void helper_##op

[PATCH 16/19] target/ppc: Clear fpstatus flags for xscvqpdp

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 627166672c..51142bd7d5 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2842,6 +2842,8 @@ void

[PATCH 12/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_INT2

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c6dc14d653..6f9a1a755e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2981,12

[PATCH 14/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_FP_HP

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index eb16fb20a9..39f0ec7431 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2791,6 +2791,8 @@ void helper_##op

[PATCH 10/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_FP

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index ceb70ed36e..8a20413a78 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2692,6 +2692,8 @@ void helper_##op

[PATCH 09/19] target/ppc: Clear fpstatus flags on VSX_CVT_INT_TO_FP

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 94029883c7..ceb70ed36e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3057,6 +3057,8 @@ void helper_##op

[PATCH 13/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_INT

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 6f9a1a755e..eb16fb20a9 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2914,22

[PATCH 07/19] target/ppc: Zero second doubleword of VSR registers for FPR insns

: Víctor Colombo --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 388337f81b..a0fa419a1f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6443,6 +6443,14 @@ static inline void get_fpr(TCGv_i64

[PATCH 08/19] target/ppc: Clear fpstatus flags on VSX_CVT_INT_TO_FP_VECTOR

Fix xscvsdqp incorrectly not clearing the FI bit. Power ISA states that xscvsdqp should always set FPSCR.FI=0 Right now, QEMU sometimes is incorrectly setting the flag to 1. Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/ppc

[PATCH 11/19] target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_INT_VECTOR

Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 8a20413a78..c6dc14d653 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3024,6 +3024,8

[PATCH 06/19] target/ppc: Set OV32 when OV is set

According to PowerISA: "OV32 is set whenever OV is implicitly set, and is set to the same value that OV is defined to be set to in 32-bit mode". This patch changes helper_update_ov_legacy to set/clear ov32 when applicable. Signed-off-by: Víctor Colombo --- target/ppc/int_helper.c |

[PATCH 05/19] target/ppc: Zero second doubleword for VSX madd instructions

In 205eb5a89e we updated most VSX instructions to zero the second doubleword, as is requested by PowerISA since v3.1. However, VSX_MADD helper was left behind unchanged, while it is also affected and should be fixed as well. This patch applies the fix for MADD instructions. Signed-off-by: Víctor

[PATCH 01/19] target/ppc: Remove extra space from s128 field in ppc_vsr_t

Very trivial rogue space removal. There are two spaces between Int128 and s128 in ppc_vsr_t struct, where it should be only one. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index

[PATCH 04/19] target/ppc: Set result to QNaN for DENBCD when VXCVI occurs

bled (VE=0) and Invalid Operation occurs (...) If the operation is an (...) or format the target FPR is set to a Quiet NaN". This was not being done in QEMU. This patch sets the result to QNaN when the instruction DENBCD causes an Invalid Operation Exception. Signed-off-by: Víctor Colombo --- tar

[PATCH 02/19] target/ppc: Remove unused xer_* macros

The macros xer_ov, xer_ca, xer_ov32, and xer_ca32 are both unused and hiding the usage of env. Remove them. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 4 1 file changed, 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 985ff86f55..6481f48087 100644 --- a

[PATCH 03/19] target/ppc: Zero second doubleword in DFP instructions

p128. This fixes the behavior for ISA 3.1 while keeping the behavior correct for previous ones. Signed-off-by: Víctor Colombo --- target/ppc/dfp_helper.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c index 5ba74b2124..b

[PATCH 00/19] Multiple ppc instructions fixes

being kept from the previous instruction, causing incorrect bits to be set, specially the non-sticky FI bit. Other patches fixes other specific situations. Víctor Colombo (19): target/ppc: Remove extra space from s128 field in ppc_vsr_t target/ppc: Remove unused xer_* macros target/ppc

Re: [PATCH v3] target/ppc: Implement new wait variants

ch ISA, and this v2 looks ok now. I didn't dive deep on the 'waiting' behavior itself, but assuming the code is the same as was before, and the new considerations regarding noop seems to be correct when compared with what the ISA says, LGTM Reviewed-by: Víctor Colombo -- Víctor Cora Colombo Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

Re: [PATCH] target/ppc: fix unreachable code in do_ldst_quad()

t: I think the indentation here is off by 1 level (missing 4 spaces)? +#endif } if (!store && unlikely(a->ra == a->rt)) { -- 2.36.1 Reviewed-by: Víctor Colombo -- Víctor Cora Colombo Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

Re: [PATCH] target/ppc: Implement new wait variants

Hello Nicholas, On 19/07/2022 08:38, Nicholas Piggin wrote: ISA v2.06 adds new variations of wait, specified by the WC field. These are not compatible with the wait 0 implementation, because they add additional conditions that cause the processor to resume, which can cause software to hang or ru

[PATCH v4 3/3] target/ppc: Implement hashstp and hashchkp

Implementation for instructions hashstp and hashchkp, the privileged versions of hashst and hashchk, which were added in Power ISA 3.1B. Signed-off-by: Víctor Colombo --- target/ppc/excp_helper.c | 2 ++ target/ppc/helper.h| 2 ++ target/ppc/insn32

[PATCH v4 1/3] target/ppc: Add HASHKEYR and HASHPKEYR SPRs

s its responsability to do so. We initialize it with 0 for qemu-softmmu, and set a random 64 bits value for linux-user. Signed-off-by: Víctor Colombo --- Is the way I did the random number generation ok? --- target/ppc/cpu.h | 2 ++ target/ppc/cpu_init.c | 28 2

[PATCH v4 2/3] target/ppc: Implement hashst and hashchk

Implementation for instructions hashst and hashchk, which were added in Power ISA 3.1B. It was decided to implement the hash algorithm from ground up in this patch exactly as described in Power ISA. Signed-off-by: Víctor Colombo --- target/ppc/excp_helper.c | 82

[PATCH v4 0/3] Implement Power ISA 3.1B hash insns

R_HASHKEYR - Drop RFC tag [1] https://eprint.iacr.org/2013/404.pdf Víctor Colombo (3): target/ppc: Add HASHKEYR and HASHPKEYR SPRs target/ppc: Implement hashst and hashchk target/ppc: Implement hashstp and hashchkp target/ppc/cpu.h | 2 + targ

Re: [RFC PATCH v3 0/3] Implement Power ISA 3.1B hash insns

On 15/07/2022 10:23, Daniel Henrique Barboza wrote: On 7/13/22 13:54, Víctor Colombo wrote: This patch series implements the 4 instructions added in Power ISA 3.1B: - hashchk - hashst - hashchkp - hashstp To build it, you need to apply the following patches on top of master

[RFC PATCH v3 3/3] target/ppc: Implement hashstp and hashchkp

Implementation for instructions hashstp and hashchkp, the privileged versions of hashst and hashchk, which were added in Power ISA 3.1B. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 3 +++ target/ppc

[RFC PATCH v3 2/3] target/ppc: Implement hashst and hashchk

Implementation for instructions hashst and hashchk, which were added in Power ISA 3.1B. It was decided to implement the hash algorithm from ground up in this patch exactly as described in Power ISA. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 1 + target/ppc

[RFC PATCH v3 1/3] linux-headers/asm-powerpc/kvm.h: Add HASHKEYR and HASHPKEYR in headers

Linux KVM currently does not export these registers. Create placeholders for them to allow implementing hashchk(p) and hashst(p) instructions from PowerISA 3.1B. Signed-off-by: Víctor Colombo --- linux-headers/asm-powerpc/kvm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux

[RFC PATCH v3 0/3] Implement Power ISA 3.1B hash insns

es anyone have any insight on this? v1->v2: - Split the patch in 2 - Rebase to master v2->v3: - Split patches in 3 - the new patch (patch 1) is separating the kvm header changes [Cornelia] [1] https://eprint.iacr.org/2013/404.pdf Víctor Colombo (3): linux-headers/asm-powerpc/k

Re: [RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk

On 11/07/2022 11:18, Cornelia Huck wrote: On Mon, Jul 11 2022, Víctor Colombo wrote: Implementation for instructions hashst and hashchk, which were added in Power ISA 3.1B. It was decided to implement the hash algorithm from ground up in this patch exactly as described in Power ISA. Signed

[RFC PATCH v2 2/2] target/ppc: Implement hashstp and hashchkp

Implementation for instructions hashstp and hashchkp, the privileged versions of hashst and hashchk, which were added in Power ISA 3.1B. Signed-off-by: Víctor Colombo --- linux-headers/asm-powerpc/kvm.h| 1 + target/ppc/cpu.h | 1 + target/ppc/cpu_init.c

[RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk

Implementation for instructions hashst and hashchk, which were added in Power ISA 3.1B. It was decided to implement the hash algorithm from ground up in this patch exactly as described in Power ISA. Signed-off-by: Víctor Colombo --- linux-headers/asm-powerpc/kvm.h| 2 + target/ppc

[RFC PATCH v2 0/2] Implement Power ISA 3.1B hash insns

m not sure what is the behavior here, I would expect that is the job of the OS to set the regs, but looks like KVM is not exporting them, so they are always 0 (?). Does anyone have any insight on this? v1->v2: - Split the patch in 2 - Rebase to master [1] https://eprint.iacr.org/2013/404.pdf

Re: [PATCH 1/2] util/log: Add vu to dump content of vector unit

On 08/07/2022 05:57, Kito Cheng wrote: Add new option for -d vu to dump the content of vector unit, many target has vector register, but there is no easy way to dump the content, we use this on downstream for a while to help debug, and I feel that's really useful, so I think it would be great to

Re: [RFC 5/8] static-analyzer: Enforce coroutine_fn restrictions on function pointers

On 04/07/2022 15:04, Alberto Faria wrote: On Mon, Jul 4, 2022 at 6:46 PM Víctor Colombo wrote: Yes, this line is present at the beginning of the output Is this caused by problems with the code being analyzed or is it because libclang is getting confused with something that is outside of our

Re: [RFC 5/8] static-analyzer: Enforce coroutine_fn restrictions on function pointers

On 04/07/2022 13:57, Alberto Faria wrote: Hi Víctor, On Mon, Jul 4, 2022 at 3:18 PM Víctor Colombo wrote: And I receive an exception on the line above saying that node is of type NoneType. Seems that `node = node.referenced` is setting `node` to None in this case. I was unable to understand

Re: [RFC 5/8] static-analyzer: Enforce coroutine_fn restrictions on function pointers

On 02/07/2022 08:33, Alberto Faria wrote: Alberto, hello. I was testing this patch as follows: ./static-analyzer.py build target/ppc/mmu-hash64.c @@ -627,9 +744,31 @@ def is_coroutine_fn(node: Cursor) -> bool: else: break -return node.kind == CursorKind.FUNCTION_

Re: [PATCH v2] target/ppc: Return default CPU for max CPU

chine()); +if (mc) { + return object_class_by_name(mc->default_cpu_type); +} +} +#endif + cpu_model = g_ascii_strdown(name, -1); p = ppc_cpu_lookup_alias(cpu_model); if (p) { -- 2.36.1 Reviewed-by: Víctor Colombo Best regards, -- Víctor Cora Colombo Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

[PATCH v3 09/11] target/ppc: implement addg6s

From: Matheus Ferst Implements the following Power ISA v2.06 instruction: addg6s: Add and Generate Sixes Signed-off-by: Matheus Ferst Signed-off-by: Víctor Colombo Reviewed-by: Víctor Colombo --- target/ppc/insn32.decode | 4 +++ target/ppc/translate/fixedpoint-impl.c.inc

[PATCH v3 11/11] target/ppc: implement cdtbcd

iewed-by: Richard Henderson Signed-off-by: Matheus Ferst Signed-off-by: Víctor Colombo --- target/ppc/dfp_helper.c| 26 ++ target/ppc/helper.h| 1 + target/ppc/insn32.decode | 1 + target/ppc/translate/fixed

[PATCH v3 07/11] tests/tcg/ppc64: Add mffsce test

Add mffsce test to check both the return value and the new fpscr stored in the cpu. Signed-off-by: Víctor Colombo Reviewed-by: Matheus Ferst --- tests/tcg/ppc64/Makefile.target | 1 + tests/tcg/ppc64le/Makefile.target | 1 + tests/tcg/ppc64le/mffsce.c| 37

[PATCH v3 08/11] target/ppc: Add flag for ISA v2.06 BCDA instructions

/EREF_RM.pdf [2] https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf Signed-off-by: Matheus Ferst Signed-off-by: Víctor Colombo Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 5 - target/ppc/cpu_init.c | 10 ++ 2 files changed, 10 insertions(+), 5 deletions(-) diff --git

[PATCH v3 04/11] target/ppc: Move mffsl to decodetree

Signed-off-by: Víctor Colombo Reviewed-by: Matheus Ferst --- target/ppc/insn32.decode | 1 + target/ppc/translate/fp-impl.c.inc | 38 +- target/ppc/translate/fp-ops.c.inc | 2 -- 3 files changed, 17 insertions(+), 24 deletions(-) diff --git a/target/ppc

[PATCH v3 10/11] target/ppc: implement cbcdtd

avior is undefined, we try to match the result observed in a POWER9 DD2.3. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst Signed-off-by: Víctor Colombo --- target/ppc/dfp_helper.c| 39 ++ target/ppc/helper.h| 1 + t

[PATCH v3 06/11] target/ppc: Implement mffscdrn[i] instructions

Signed-off-by: Víctor Colombo Reviewed-by: Matheus Ferst --- target/ppc/insn32.decode | 5 target/ppc/translate/fp-impl.c.inc | 41 ++ 2 files changed, 46 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 736a7c6f3f

[PATCH v3 02/11] target/ppc: Move mffscrn[i] to decodetree

Signed-off-by: Víctor Colombo Reviewed-by: Matheus Ferst --- target/ppc/insn32.decode | 8 +++ target/ppc/internal.h | 3 -- target/ppc/translate/fp-impl.c.inc | 83 +++--- target/ppc/translate/fp-ops.c.inc | 4 -- 4 files changed, 50

[PATCH v3 05/11] target/ppc: Move mffs[.] to decodetree

Signed-off-by: Víctor Colombo Reviewed-by: Matheus Ferst --- target/ppc/insn32.decode | 4 target/ppc/translate/fp-impl.c.inc | 35 +++--- target/ppc/translate/fp-ops.c.inc | 1 - 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/target

[PATCH v3 03/11] target/ppc: Move mffsce to decodetree

Signed-off-by: Víctor Colombo Reviewed-by: Matheus Ferst --- target/ppc/insn32.decode | 4 +++ target/ppc/translate/fp-impl.c.inc | 46 +++--- target/ppc/translate/fp-ops.c.inc | 2 -- 3 files changed, 20 insertions(+), 32 deletions(-) diff --git a/target

[PATCH v3 01/11] target/ppc: Fix insn32.decode style issues

Some lines in insn32.decode have inconsistent alignment when compared to others. Fix this by changing the alignment of some lines, making it more consistent throughout the file. Signed-off-by: Víctor Colombo Reviewed-by: Richard Henderson --- target/ppc/insn32.decode | 24

[PATCH v3 00/11] target/ppc: BCDA and mffscdrn implementations

: Add flag for ISA v2.06 BCDA instructions target/ppc: implement addg6s target/ppc: implement cbcdtd target/ppc: implement cdtbcd Víctor Colombo (7): target/ppc: Fix insn32.decode style issues target/ppc: Move mffscrn[i] to decodetree target/ppc: Move mffsce to decodetree target/ppc: Move

Re: [PATCH 7/7] target/ppc: use int128.h methods in vsubcuq

RM_300(bcdtrunc, 0, 20), -GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300), +GEN_VXFORM_300(bcdutrunc, 0, 21), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), GEN_VXFORM(vpkuhum, 7, 0), -- 2.25.1 Reviewed-by: Víctor Colombo -- Víctor Cora Colombo Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

Re: [PATCH 5/7] target/ppc: use int128.h methods in vsubuqm

EN_VXFORM_300(bcdtrunc, 0, 20), GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM(vsl, 2, 7), -- 2.25.1 Reviewed-by: Víctor Colombo -- Víctor Cora Colombo Instituto de P

Re: [PATCH 2/7] target/ppc: use int128.h methods in vadduqm

C_207, PPC2_ISA300), -- 2.25.1 Reviewed-by: Víctor Colombo -- Víctor Cora Colombo Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

Re: [PATCH 1/7] target/ppc: use int128.h methods in vpmsumd

no need to access the elements in any particular order, and move the instruction to decodetree. Signed-off-by: Matheus Ferst Reviewed-by: Víctor Colombo -- Víctor Cora Colombo Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

Re: [PATCH 4/7] target/ppc: use int128.h methods in vaddcuq

0, 20, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), -- 2.25.1 Reviewed-by: Víctor Colombo -- Víctor Cora Colombo Instituto de Pesquisas ELD

Re: [PATCH 6/7] target/ppc: use int128.h methods in vsubecuq and vsubeuqm

M_300(bcdtrunc, 0, 20), GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300), -GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), GEN_VXFORM(vpkuhum, 7, 0), -- 2.25.1 Reviewed-by: Víctor Colombo -- Víctor Cora Colombo Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>

Re: [PATCH 3/7] target/ppc: use int128.h methods in vaddecuq and vaddeuqm

subsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_207(vaddcuq, 0, 5), -GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_20

Re: [PATCH] target/riscv: fix user-mode build issue because mhartid

On 27/06/2022 06:40, Rahul Pathak wrote: mhartid csr is not available in user-mode code path and user-mode build fails because of its reference in riscv_cpu_realize function Signed-off-by: Rahul Pathak --- target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/ri

[PATCH] target/ppc: Change FPSCR_* to follow POWER ISA numbering convention

make then fit in 80 columns Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 72 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 6d78078f37..c78f64cced 100644 --- a/target/ppc/cpu.h ++

[RFC PATCH] target/ppc: Implement hashst(p) and hashchk(p) instructions

Implementation for instructions hashst, hashchk, and its privileged versions. It was decided to implement the hash algorithm from ground up in this patch exactly as described in Power ISA. Signed-off-by: Víctor Colombo --- RFC because I need some feedback on if the approach of implementing

[PATCH RESEND v2 11/11] target/ppc: implement cdtbcd

iewed-by: Richard Henderson Signed-off-by: Matheus Ferst Signed-off-by: Víctor Colombo --- target/ppc/dfp_helper.c| 26 ++ target/ppc/helper.h| 1 + target/ppc/insn32.decode | 1 + target/ppc/translate/fixed

[PATCH RESEND v2 10/11] target/ppc: implement cbcdtd

avior is undefined, we try to match the result observed in a POWER9 DD2.3. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst Signed-off-by: Víctor Colombo --- target/ppc/dfp_helper.c| 39 ++ target/ppc/helper.h| 1 + t

[PATCH RESEND v2 06/11] target/ppc: Implement mffscdrn[i] instructions

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 5 target/ppc/translate/fp-impl.c.inc | 41 ++ 2 files changed, 46 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 8954a13d6b..da507758b8 100644 --- a

[PATCH RESEND v2 04/11] target/ppc: Move mffsl to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 1 + target/ppc/translate/fp-impl.c.inc | 38 +- target/ppc/translate/fp-ops.c.inc | 2 -- 3 files changed, 17 insertions(+), 24 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc

[PATCH RESEND v2 02/11] target/ppc: Move mffscrn[i] to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 8 +++ target/ppc/internal.h | 3 -- target/ppc/translate/fp-impl.c.inc | 83 +++--- target/ppc/translate/fp-ops.c.inc | 4 -- 4 files changed, 50 insertions(+), 48 deletions(-) diff

[PATCH RESEND v2 05/11] target/ppc: Move mffs[.] to decodetree

Signed-off-by: Víctor Colombo --- target/ppc/insn32.decode | 4 target/ppc/translate/fp-impl.c.inc | 35 +++--- target/ppc/translate/fp-ops.c.inc | 1 - 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/target/ppc/insn32.decode b/target

[PATCH RESEND v2 07/11] tests/tcg/ppc64: Add mffsce test

Add mffsce test to check both the return value and the new fpscr stored in the cpu. Signed-off-by: Víctor Colombo --- tests/tcg/ppc64/Makefile.target | 1 + tests/tcg/ppc64le/Makefile.target | 1 + tests/tcg/ppc64le/mffsce.c| 37 +++ 3 files changed, 39

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