On Mon, 6 Nov 2023 15:05:33 +0100 Igor Mammedov (IM) wrote:
> it might be worth mentioning that QEMU impl. uses 32 bit registers and
> can correctly handle 32 bit access only, while 16 (or any other) bit access
> to 32 bit registers won't actually work.
>
> ex:
> pl011_write()
>...
>swi
Public bug reported:
On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3,
which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers.
However, setting that HCR bit has no effect and accesses to those ID
registers are not trapped to EL2 with an EC syndrome value of 0x18.
**
Public bug reported:
The following happens with QEMU-0.14-rc2. QEMU-0.13 did not have this
problem.
A guest operating system running inside an SVM VM contains the following code
sequence:
c02b: fb sti
c02c: 0f 35 sysexit
The follow
