[PATCH v6 5/5] target/riscv: Add Smrnmi cpu extension.

This adds the properties for ISA extension Smrnmi. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 98e6940e93..7ee7b9c4ee 100644 --- a/target/riscv/cpu.c +++ b/target

[PATCH v6 2/5] target/riscv: Handle Smrnmi interrupt and exception.

signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 18 include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c| 11 + target/riscv/cpu.h| 6 +++ target/riscv/cpu_bits.h | 12 ++ target/riscv

[PATCH v6 3/5] target/riscv: Add Smrnmi CSRs.

The Smrnmi extension adds the `MNSCRATCH`, `MNEPC`, `MNCAUSE`, `MNSTATUS` CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 11 ++ target/riscv/csr.c

[PATCH v6 1/5] target/riscv: Add `ext_smrnmi` in the RISCVCPUConfig.

The boolean variable `ext_smrnmi` is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv

[PATCH v6 4/5] target/riscv: Add Smrnmi mnret instruction.

This patch adds a new instruction `mnret`. `mnret` is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target

[PATCH v6 0/5] target/riscv: Add Smrnmi support.

commits for convenience of review. * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts. Tommy Wu (5): target/riscv: Add `ext_smrnmi` in the RISCVCPUConfig. target/riscv: Handle Smrnmi interrupt and exception. target/riscv: Add Smrnmi CSRs. target/riscv: Add Smrnmi mnret

Re: [PATCH v5 4/5] target/riscv: Add Smrnmi mnret instruction.

On Fri, Aug 30, 2024 at 7:42 AM Alistair Francis wrote: > > On Fri, Aug 30, 2024 at 2:12 AM Tommy Wu wrote: > > > > On Mon, Aug 19, 2024 at 11:49 AM Alistair Francis > > wrote: > > > > > > On Fri, Aug 9, 2024 at 6:12 PM Tommy Wu wrote: > > >

Re: [PATCH v5 4/5] target/riscv: Add Smrnmi mnret instruction.

On Mon, Aug 19, 2024 at 11:49 AM Alistair Francis wrote: > > On Fri, Aug 9, 2024 at 6:12 PM Tommy Wu wrote: > > > > This patch adds a new instruction `mnret`. `mnret` is an M-mode-only > > instruction that uses the values in `mnepc` and `mnstatus` to return to the > &

Re: [PATCH v5 2/5] target/riscv: Handle Smrnmi interrupt and exception.

On Thu, Aug 15, 2024 at 9:40 AM Alvin Che-Chia Chang(張哲嘉) wrote: > > Hi Tommy, > > > -Original Message- > > From: qemu-riscv-bounces+alvinga=andestech@nongnu.org > > On Behalf Of > > Tommy Wu > > Sent: Friday, August 9, 2024 4:12 PM

Re: [RFC PATCH 3/3] target/riscv: add Smdbltrp extension support

a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -545,6 +545,7 @@ > #define MSTATUS_SDT 0x0100 /* Ssdbltrp extension */ > #define MSTATUS_GVA 0x40ULL > #define MSTATUS_MPV 0x80ULL > +#define MSTATUS_MDT 0x2000ULL /* Sm

Re: [RFC PATCH 2/3] target/riscv: add Ssdbltrp extension support

target_ulong val) > { > uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | > - HENVCFG_ADUE); > +HENVCFG_ADUE | HENVCFG_DTE); > uint64_t valh = (uint64_t)val << 32; > RISCVException ret; > > @@ -4801,7 +4825,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_VSATP] = { "vsatp", hmode, read_vsatp,write_vsatp, >.min_priv_ver = PRIV_VERSION_1_12_0 > }, > > -[CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, > write_mtval2, > +[CSR_MTVAL2] = { "mtval2", dbltrp_hmode, read_mtval2, > write_mtval2, >.min_priv_ver = PRIV_VERSION_1_12_0 > }, > [CSR_MTINST] = { "mtinst", hmode, read_mtinst, > write_mtinst, >.min_priv_ver = PRIV_VERSION_1_12_0 > }, > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index f414aaebdb..468ee58a00 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -289,6 +289,17 @@ target_ulong helper_sret(CPURISCVState *env) > get_field(mstatus, MSTATUS_SPIE)); > mstatus = set_field(mstatus, MSTATUS_SPIE, 1); > mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); > +if (riscv_cpu_cfg(env)->ext_ssdbltrp) { > +if (env->virt_enabled) { > +if (get_field(env->henvcfg, HENVCFG_DTE)) { > +mstatus = set_field(mstatus, MSTATUS_SDT, 0); > +} > +} else { > +if (get_field(env->menvcfg, MENVCFG_DTE)) { > +mstatus = set_field(mstatus, MSTATUS_SDT, 0); > +} > +} > +} > if (env->priv_ver >= PRIV_VERSION_1_12_0) { > mstatus = set_field(mstatus, MSTATUS_MPRV, 0); > } > -- > 2.43.0 > > Thanks for the patchset. Best Regards, Tommy Wu.

[PATCH v5 5/5] target/riscv: Add Smrnmi cpu extension.

This adds the properties for ISA extension Smrnmi. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 98e6940e93..7ee7b9c4ee 100644 --- a/target/riscv/cpu.c +++ b/target

[PATCH v5 0/5] target/riscv: Add Smrnmi support.

specification. v2 * split up the series into more commits for convenience of review. * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts. Tommy Wu (5): target/riscv: Add `ext_smrnmi` in the RISCVCPUConfig. target/riscv: Handle Smrnmi interrupt and exception. target/riscv: Add Smrnmi

[PATCH v5 3/5] target/riscv: Add Smrnmi CSRs.

The Smrnmi extension adds the `MNSCRATCH`, `MNEPC`, `MNCAUSE`, `MNSTATUS` CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 11 ++ target/riscv/csr.c

[PATCH v5 1/5] target/riscv: Add `ext_smrnmi` in the RISCVCPUConfig.

The boolean variable `ext_smrnmi` is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 8b272fb826

[PATCH v5 2/5] target/riscv: Handle Smrnmi interrupt and exception.

signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 18 include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c| 11 + target/riscv/cpu.h| 6 +++ target/riscv/cpu_bits.h | 12 ++ target/riscv

[PATCH v5 4/5] target/riscv: Add Smrnmi mnret instruction.

This patch adds a new instruction `mnret`. `mnret` is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target

Re: [PATCH v4 1/4] target/riscv: Add Smrnmi cpu extension.

On Mon, Jun 12, 2023 at 1:04 PM Alistair Francis wrote: > > On Thu, Jun 8, 2023 at 5:25 PM Tommy Wu wrote: > > > > Signed-off-by: Frank Chang > > Signed-off-by: Tommy Wu > > --- > > hw/riscv/riscv_hart.c | 21 + >

Re: [PATCH v4 1/4] target/riscv: Add Smrnmi cpu extension.

On Thu, Jun 8, 2023 at 5:52 PM Andrew Jones wrote: > > > Please add a commit message to all patches of the series. > > Another comment below. Thanks for the suggestion, I'll add commit messages to all patches in the v5 patches. > > On Thu, Jun 08, 2023 at 12:23:

Re: [PATCH v4 0/4] target/riscv: Add Smrnmi support.

On Thu, Jun 8, 2023 at 5:43 PM Andrew Jones wrote: > > On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote: > > This patchset added support for Smrnmi Extension in RISC-V. > > > > There are four new CSRs and one new instruction added to allow NMI to be > >

[PATCH] target/riscv: Align the AIA model to v1.0 ratified spec

According to the new spec, when vsiselect has a reserved value, attempts from M-mode or HS-mode to access vsireg, or from VS-mode to access sireg, should preferably raise an illegal instruction exception. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- target/riscv/csr.c | 7 +-- 1

Re: [PATCH v5 0/3] Implement the watchdog timer of HiFive 1 rev b.

Hi Alistair, Thanks for the suggestion! I've rebased and sent patch v6. Best Regards, Tommy On Thu, Jun 22, 2023 at 10:10 AM Alistair Francis wrote: > On Fri, Jun 9, 2023 at 2:46 AM Tommy Wu wrote: > > > > The HiFive 1 rev b includes a watchdog module based on a 32-

[PATCH v6 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.

Create the AON device when we realize the sifive_e machine. This patch only implemented the functionality of the watchdog timer, not all the functionality of the AON device. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- hw/riscv/Kconfig| 1

[PATCH v6 3/3] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e

Add some simple tests of the watchdog timer in the always-on domain device of HiFive 1 rev b. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang Acked-by: Thomas Huth Acked-by: Alistair Francis --- tests/qtest/meson.build | 3 + tests/qtest/sifive-e-aon-watchdog-test.c | 450

[PATCH v6 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.

The watchdog timer is in the always-on domain device of HiFive 1 rev b, so this patch added the AON device to the sifive_e machine. This patch only implemented the functionality of the watchdog timer. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang Acked-by: Alistair Francis --- hw/misc

[PATCH v6 0/3] Implement the watchdog timer of HiFive 1 rev b.

device state in the SoC. Changes since v5 ( Thank Alistair for the feedback ): - Rebase to the riscv-to-apply.next branch. Tommy Wu (3): hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. tests/qtest: sifive-e

Re: [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml.

. Best Regards, Tommy On Thu, May 25, 2023 at 10:33 AM Alistair Francis wrote: > On Tue, May 23, 2023 at 9:46 PM Tommy Wu wrote: > > > > When we change the cpu extension state after the cpu is > > realized, we cannot print the value of some CSRs in the remote > >

[PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.

According to the `The RISC-V Advanced Interrupt Architecture` document, if register `mmsiaddrcfgh` of the domain has bit L set to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang

Re: [PATCH v4 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.

Hi Phil, Thanks for all the suggestions, I'll send patch v5 to fix all the issues. Best Regards, Tommy On Thu, May 25, 2023 at 8:05 PM Philippe Mathieu-Daudé wrote: > Hi Tommy, > > On 23/5/23 10:49, Tommy Wu wrote: > > The watchdog timer is in the always-on domain devi

[PATCH v5 3/3] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e

Add some simple tests of the watchdog timer in the always-on domain device of HiFive 1 rev b. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang Acked-by: Thomas Huth --- tests/qtest/meson.build | 3 + tests/qtest/sifive-e-aon-watchdog-test.c | 450 +++ 2

[PATCH v5 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.

Create the AON device when we realize the sifive_e machine. This patch only implemented the functionality of the watchdog timer, not all the functionality of the AON device. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- hw/riscv/Kconfig| 1 + hw/riscv/sifive_e.c

[PATCH v5 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.

The watchdog timer is in the always-on domain device of HiFive 1 rev b, so this patch added the AON device to the sifive_e machine. This patch only implemented the functionality of the watchdog timer. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- hw/misc/Kconfig| 3

[PATCH v5 0/3] Implement the watchdog timer of HiFive 1 rev b.

device state in the SoC. Tommy Wu (3): hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e hw/misc/Kconfig

[PATCH v4 3/4] target/riscv: Handle Smrnmi interrupt and exception.

Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu_helper.c | 57 +++ 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index da477b6c99..1a926bb661 100644 --- a/target

[PATCH v4 2/4] target/riscv: Add Smrnmi CSRs.

Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 11 ++ target/riscv/csr.c | 82 + 4 files changed, 102 insertions(+) diff --git a/target/riscv

[PATCH v4 1/4] target/riscv: Add Smrnmi cpu extension.

Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 21 + include/hw/riscv/riscv_hart.h | 4 target/riscv/cpu.c| 13 + target/riscv/cpu.h| 7 +++ target/riscv/cpu_bits.h | 12

[PATCH v4 4/4] target/riscv: Add Smrnmi mnret instruction.

Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/helper.h | 1 + target/riscv/insn32.decode| 3 ++ .../riscv/insn_trans/trans_privileged.c.inc | 12 + target/riscv/op_helper.c | 49 +++ 4

[PATCH v4 0/4] target/riscv: Add Smrnmi support.

newest version of Smrnmi extension specification. v2 * split up the series into more commits for convenience of review. * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts. Tommy Wu (4): target/riscv: Add Smrnmi cpu extension. target/riscv: Add Smrnmi CSRs. target/riscv

Re: [PATCH v3 1/4] target/riscv: Add Smrnmi cpu extension.

Hi Daniel, Thanks for all the suggestions ! I'll send patch v4 and fix all the issues. On Thu, May 25, 2023 at 8:29 PM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: > > > On 5/22/23 10:11, Tommy Wu wrote: > > Signed-off-by: Frank Chang &

Re: [PATCH 2/2] hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu.

Hi Weiwei Li, You're right, it seems that we need to add a check in riscv_imsic.c Thanks for the advice! Best Regards, Tommy On Wed, May 24, 2023 at 10:35 AM Weiwei Li wrote: > > On 2023/5/24 09:51, Tommy Wu wrote: > > Hi Weiwei Li, > > Yes, you're right, `r

Re: [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml.

use we've record this value in the ` cpu->dyn_csr_base_reg`. Best Regards, Tommy On Wed, May 24, 2023 at 10:10 AM Weiwei Li wrote: > > On 2023/5/24 09:59, Tommy Wu wrote: > > Hi Weiwei Li, > > > > `dyn_csr_base_reg` will be used in `riscv_refresh_dynamic_

Re: [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml.

19:44, Tommy Wu wrote: > > When we change the cpu extension state after the cpu is > > realized, we cannot print the value of some CSRs in the remote > > gdb debugger. The root cause is that the dynamic CSR xml is > > generated when the cpu is realized. > > > >

Re: [PATCH 2/2] hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu.

gt; On 2023/5/23 19:44, Tommy Wu wrote: > > Originally, when we set the ext_smaia to true, we still cannot print the > > AIA CSRs in the remote gdb debugger, because the dynamic CSR xml is > > generated when the cpu is realized. > > > > This patch refreshes the dynamic C

[PATCH 2/2] hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu.

gdb debugger. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- hw/intc/riscv_imsic.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index fea3385b51..97a51d535b 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -350,6

[PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml.

. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- target/riscv/cpu.h | 2 ++ target/riscv/gdbstub.c | 12 2 files changed, 14 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de7e43126a..dc8e592275 100644 --- a/target/riscv/cpu.h +++ b/target/riscv

[PATCH 0/2] Refresh the dynamic CSR xml after updating the state of the cpu.

IMSIC. Tommy Wu (2): target/riscv: Add a function to refresh the dynamic CSRs xml. hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu. hw/intc/riscv_imsic.c | 4 target/riscv/cpu.h | 2 ++ target/riscv/gdbstub.c | 12 3 files changed, 18

[PATCH v4 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.

The watchdog timer is in the always-on domain device of HiFive 1 rev b, so this patch added the AON device to the sifive_e machine. This patch only implemented the functionality of the watchdog timer. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- hw/misc/Kconfig| 3

[PATCH v4 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.

Create the AON device when we realize the sifive_e machine. This patch only implemented the functionality of the watchdog timer, not all the functionality of the AON device. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- hw/riscv/Kconfig| 1 + hw/riscv/sifive_e.c

[PATCH v4 3/3] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e

Add some simple tests of the watchdog timer in the always-on domain device of HiFive 1 rev b. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- tests/qtest/meson.build | 3 + tests/qtest/sifive-e-aon-watchdog-test.c | 450 +++ 2 files changed, 453

[PATCH v4 0/3] Implement the watchdog timer of HiFive 1 rev b.

SPDX identifier in QTEST. - Use libqtest.h in QTEST. - Let the statements on one line as long as they still fit into 80 columns. Tommy Wu (3): hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. tests/qtest

Re: [PATCH v3 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.

Hi Alistair, Sorry for the very late reply. Thanks for the code review! I'll send patch v4 to fix this issue. On Wed, Dec 7, 2022 at 12:02 PM Alistair Francis wrote: > On Wed, Nov 30, 2022 at 11:56 AM Tommy Wu wrote: > > > > The watchdog timer is in the always-on domain de

Re: [PATCH v3 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e

Hi Thomas, Sorry for the very late reply. Thanks for the code review! I'll send patch v4 to fix these issues. On Wed, Nov 30, 2022 at 7:29 PM Thomas Huth wrote: > On 30/11/2022 02.54, Tommy Wu wrote: > > Add some simple tests of the watchdog timer in the always-on domain > dev

[PATCH v3 2/4] target/riscv: Add Smrnmi CSRs.

Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 11 ++ target/riscv/csr.c | 82 + 4 files changed, 102 insertions(+) diff --git a/target/riscv

[PATCH v3 3/4] target/riscv: Handle Smrnmi interrupt and exception.

Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu_helper.c | 60 +++ 1 file changed, 55 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index cc7898f103..7bdea0d2ca 100644 --- a/target

[PATCH v3 0/4] target/riscv: Add Smrnmi support.

series into more commits for convenience of review. * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts. Tommy Wu (4): target/riscv: Add Smrnmi cpu extension. target/riscv: Add Smrnmi CSRs. target/riscv: Handle Smrnmi interrupt and exception. target/riscv: Add Smrnmi mnret

[PATCH v3 1/4] target/riscv: Add Smrnmi cpu extension.

Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 21 + include/hw/riscv/riscv_hart.h | 4 target/riscv/cpu.c| 14 ++ target/riscv/cpu.h| 7 +++ target/riscv/cpu_bits.h | 12

[PATCH v3 4/4] target/riscv: Add Smrnmi mnret instruction.

Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/helper.h | 1 + target/riscv/insn32.decode| 3 ++ .../riscv/insn_trans/trans_privileged.c.inc | 12 + target/riscv/op_helper.c | 51 +++ 4

Re: [PATCH] hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.

Thank Edgar E. Iglesias for the advice. I can submit another patch to do that. On Fri, May 19, 2023 at 2:39 PM Edgar E. Iglesias wrote: > > On Fri, May 19, 2023 at 8:21 AM Tommy Wu wrote: > >> When we receive a packet from the xilinx_axienet and then try to s2mem >> thro

[PATCH] hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.

axienet_eth_rx_notify. This patch checks the DMASR.HALTED state when we try to push data from xilinx axi-enet to xilinx axi-dma. When the DMASR.HALTED is asserted, we will not keep pushing the data and then prevent the infinte loop. Signed-off-by: Tommy Wu --- hw/dma/xilinx_axidma.c | 11

[PATCH v3 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e

Add some simple tests of the watchdog timer in the always-on domain device of HiFive 1 rev b. Signed-off-by: Tommy Wu --- tests/qtest/meson.build | 3 + tests/qtest/sifive-e-aon-watchdog-test.c | 650 +++ 2 files changed, 653 insertions(+) create mode

[PATCH v3 0/3] Implement the watchdog timer of HiFive 1 rev b.

at the top of the code block. Changes since v2 ( Thank Alistair for the feedback ): - Delete the declaration and definition of the create function. Tommy Wu (3): hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev

[PATCH v3 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.

The watchdog timer is in the always-on domain device of HiFive 1 rev b, so this patch added the AON device to the sifive_e machine. This patch only implemented the functionality of the watchdog timer. Signed-off-by: Tommy Wu --- hw/misc/Kconfig| 3 + hw/misc/meson.build

[PATCH v3 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.

Create the AON device when we realize the sifive_e machine. This patch only implemented the functionality of the watchdog timer, not all the functionality of the AON device. Signed-off-by: Tommy Wu --- hw/riscv/Kconfig| 1 + hw/riscv/sifive_e.c | 13 +++-- include

Re: [PATCH 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.

! Regards, Tommy On Mon, Oct 10, 2022 at 10:27 AM Alistair Francis wrote: > On Thu, Sep 22, 2022 at 6:45 PM Tommy Wu wrote: > > > > Create the AON device when we realize the sifive_e machine. > > This patch only implemented the functionality of the watchdog timer,

Re: [PATCH 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.

his in patch v2. On Mon, Oct 10, 2022 at 10:25 AM Alistair Francis wrote: > On Thu, Sep 22, 2022 at 6:43 PM Tommy Wu wrote: > > > > The watchdog timer is in the always-on domain device of HiFive 1 rev b, > > so this patch added the AON device to the sifive_e machine. This

[PATCH v2 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e

Add some simple tests of the watchdog timer in the always-on domain device of HiFive 1 rev b. Signed-off-by: Tommy Wu --- tests/qtest/meson.build | 3 + tests/qtest/sifive-e-aon-watchdog-test.c | 650 +++ 2 files changed, 653 insertions(+) create mode

[PATCH v2 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.

Create the AON device when we realize the sifive_e machine. This patch only implemented the functionality of the watchdog timer, not all the functionality of the AON device. Signed-off-by: Tommy Wu --- hw/riscv/Kconfig| 1 + hw/riscv/sifive_e.c | 13 +++-- include

[PATCH v2 0/3] Implement the watchdog timer of HiFive 1 rev b.

at the top of the code block. Tommy Wu (3): hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e hw/misc/Kconfig

[PATCH v2 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.

The watchdog timer is in the always-on domain device of HiFive 1 rev b, so this patch added the AON device to the sifive_e machine. This patch only implemented the functionality of the watchdog timer. Signed-off-by: Tommy Wu --- hw/misc/Kconfig| 3 + hw/misc/meson.build

[PATCH 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e

Add some simple tests of the watchdog timer in the always-on domain device of HiFive 1 rev b. Signed-off-by: Tommy Wu --- tests/qtest/meson.build | 3 + tests/qtest/sifive-e-aon-watchdog-test.c | 400 +++ 2 files changed, 403 insertions(+) create mode

[PATCH 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.

The watchdog timer is in the always-on domain device of HiFive 1 rev b, so this patch added the AON device to the sifive_e machine. This patch only implemented the functionality of the watchdog timer. Signed-off-by: Tommy Wu --- hw/misc/Kconfig| 3 + hw/misc/meson.build

[PATCH 0/3] Implement the watchdog timer of HiFive 1 rev b.

functionality of the AON device. You can test the patchset by the QTest tests/qtest/sifive-e-aon-watchdog-test.c Tommy Wu (3): hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. tests/qtest: sifive-e-aon-watchdog-test.c

[PATCH 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.

Create the AON device when we realize the sifive_e machine. This patch only implemented the functionality of the watchdog timer, not all the functionality of the AON device. Signed-off-by: Tommy Wu --- hw/riscv/Kconfig| 1 + hw/riscv/sifive_e.c | 5 +++-- include/hw/riscv

Re: [PATCH] include/hw/riscv/sifive_e.h: Fix the type of parent_obj of SiFiveEState.

To the maintainers: Thank Alistair and Jim for the review. Bernhard Beschow sent the same patch : https://lists.gnu.org/archive/html/qemu-riscv/2022-09/msg00126.html It seems that this simple patch is helpful. Could you help us to merge this patch? Thanks for your great help! Regards, Tommy Wu

[PATCH] include/hw/riscv/sifive_e.h: Fix the type of parent_obj of SiFiveEState.

Fix the type of parent_obj of SiFiveEState from 'SysBusDevice' to 'MachineState'. Because the parent of SiFiveEState is 'MachineState'. Signed-off-by: Tommy Wu --- include/hw/riscv/sifive_e.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a