Re: [PATCH v6 0/7] Add ARM Cortex-R52 CPU

On 06.12.22 11:39, Philippe Mathieu-Daudé wrote: On 6/12/22 11:24, tobias.roeh...@rwth-aachen.de wrote: From: Tobias Röhmel v6: patch 5: - I'm freeing the PRBAR/... strings explicitly now since    I don't know how to use autofree in this setup correctly.    Maybe {} around the part were th

Re: [PATCH v3 7/9] target/arm: Add PMSAv8r registers

Thank you very much for the review! I have a few questions: On 27.09.22 15:50, Peter Maydell wrote: On Sat, 20 Aug 2022 at 15:19, wrote: From: Tobias Röhmel Signed-off-by: Tobias Röhmel --- target/arm/cpu.h| 10 +++ target/arm/helper.c | 171

Re: [PATCH v2 0/9] Add Cortex-R52

On 18.07.22 13:54, Tobias Roehmel wrote: v2: PATCH 1: I have left the flag in for now because there there is a lot of use for it in the MPU translation code. The PMSAv8r differs in quite a view ways from the implementation in the Cortex-M. I think using !ARM_FEATURE_M in all of those cases

[PATCH v2 8/9] target/arm: Add PMSAv8r functionality

From: Tobias Röhmel Add PMSAv8r translation that is used by the ARM Cortex-R52. Signed-off-by: Tobias Röhmel --- target/arm/ptw.c | 171 +-- 1 file changed, 150 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c4

[PATCH v2 5/9] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup

From: Tobias Röhmel Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup to prepare for the Cortex-R52 MPU which uses and combines cache attributes of different translation levels. Signed-off-by: Tobias Röhmel --- target/arm/internals.h | 13 +++-- target/arm/m_helper.c | 3 ++-

[PATCH v2 1/9] target/arm: Add ARM_FEATURE_V8_R

From: Tobias Röhmel This flag is necessary to add features for the Cortex-R52. Signed-off-by: Tobias Röhmel --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df677b2d5d..86e06116a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/c

[PATCH v2 9/9] target/arm: Add ARM Cortex-R52 cpu

From: Tobias Röhmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias Röhmel --- target/arm/cpu_tcg.c | 42 ++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c ind

[PATCH v2 4/9] target/arm: Make stage_2_format for cache attributes optional

From: Tobias Röhmel The Cortex-R52 has a 2 stage MPU translation process but doesn't have the FEAT_S2FWB feature. This makes it neccessary to allow for the old cache attribut combination. This is facilitated by changing the control path of combine_cacheattrs instead of failing if the second ca

[PATCH v2 2/9] target/arm: Don't add all MIDR aliases for Cortex-R

From: Tobias Röhmel Cortex-R52 has the MPUIR register which has the same encoding has the MIDR alias with opc2=4. So we only add that alias when we are not realizing a Cortex-R. Signed-off-by: Tobias Röhmel --- target/arm/helper.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions

[PATCH v2 6/9] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32

From: Tobias Röhmel ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias Röhmel --- target/ar

[PATCH v2 3/9] target/arm: Make RVBAR available for all ARMv8 CPUs

From: Tobias Röhmel Signed-off-by: Tobias Röhmel --- target/arm/cpu.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b5d535788..9007768418 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -258,6 +258,10 @@ static void a

[PATCH v2 0/9] Add Cortex-R52

v2: PATCH 1: I have left the flag in for now because there there is a lot of use for it in the MPU translation code. The PMSAv8r differs in quite a view ways from the implementation in the Cortex-M. I think using !ARM_FEATURE_M in all of those cases might run into problems down the road when new

[PATCH v2 7/9] target/arm: Add PMSAv8r registers

From: Tobias Röhmel Signed-off-by: Tobias Röhmel --- target/arm/cpu.h| 10 +++ target/arm/helper.c | 171 2 files changed, 181 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 86e06116a9..632d0d13c6 100644 --- a/target/arm/c

[PATCH 10/11] target/arm: Make SPSR_hyp accessible for Cortex-R52

From: Tobias Röhmel The Cortex-R52 can access SPSR_hyp from hypervisor mode as discussed here: https://github.com/zephyrproject-rtos/zephyr/issues/47330 Signed-off-by: Tobias Röhmel --- target/arm/op_helper.c | 8 target/arm/translate.c | 5 +++-- 2 files changed, 11 insertions(+), 2

[PATCH 05/11] target/arm: Make stage_2_format for cache attributes optional

From: Tobias Röhmel The Cortex-R52 has a 2 stage MPU translation process but doesn't have the FEAT_S2FWB feature. This makes it neccessary to allow for the old cache attribut combination. This is facilitated by changing the control path of combine_cacheattrs instead of failing if the second ca

[PATCH 07/11] target/arm: Enable TTBCR_EAE for ARM_FEATURE_V8_R

From: Tobias Röhmel Enable TTBCR_EAE during reset since it's always set to 1 for Cortex-R52. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias Röhmel --- target/arm/cpu.c | 3 +++ 1 file change

[PATCH 00/11] Add Cortex-R52

These patches add the ARM Cortex-R52. The biggest addition is an implementation of the armv8-r MPU. The last patch adds a machine that combines the new core with an UART and a GIC. This machine can run many samples of the Zephyr OS. All information is taken from: - ARM Cortex-R52 TRM revision r1p3

[PATCH 03/11] target/arm: Add v8R MIDR register

From: Tobias Röhmel This register is used by the ARM Cortex-R52. Signed-off-by: Tobias Röhmel --- target/arm/helper.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6457e6301c..bdf1df37d5 100644 --- a/target/arm

[PATCH 11/11] hw/arm: Add R52 machine

From: Tobias Röhmel Signed-off-by: Tobias Röhmel --- configs/devices/arm-softmmu/default.mak | 1 + hw/arm/Kconfig | 5 + hw/arm/meson.build | 1 + hw/arm/r52_machine.c| 133 +++ hw/arm/r52_virt.c

[PATCH 02/11] target/arm: Add ARM Cortex-R52 cpu

From: Tobias Röhmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias Röhmel --- target/arm/cpu_tcg.c | 54 1 file changed, 54 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c i

[PATCH 08/11] target/arm Add PMSAv8r registers

From: Tobias Röhmel Signed-off-by: Tobias Röhmel --- target/arm/cpu.h| 10 +++ target/arm/helper.c | 171 2 files changed, 181 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 86e06116a9..632d0d13c6 100644 --- a/target/arm/c

[PATCH 09/11] target/arm: Add PMSAv8r functionality

From: Tobias Röhmel Add PMSAv8r translation that is used by the ARM Cortex-R52. Signed-off-by: Tobias Röhmel --- target/arm/ptw.c | 171 +-- 1 file changed, 150 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c4

[PATCH 04/11] target/arm: Make RVBAR available for non AARCH64 CPUs

From: Tobias Röhmel The ARM Cortex-R52 is not AARCH64 but uses RVBAR. Signed-off-by: Tobias Röhmel --- target/arm/cpu.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b5d535788..2c26a5387d 100644 --- a/target/arm/cpu.c +++ b

[PATCH 06/11] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup

From: Tobias Röhmel Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup to prepare for the Cortex-R52 MPU which uses and combines cache attributes of different translation levels. Signed-off-by: Tobias Röhmel --- target/arm/internals.h | 13 +++-- target/arm/m_helper.c | 3 ++-

[PATCH 01/11] target/arm: Add ARM_FEATURE_V8_R

From: Tobias Röhmel This flag is necessary to add features for the Cortex-R52. Signed-off-by: Tobias Röhmel --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df677b2d5d..86e06116a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/c