0, 8);
+ssi_transfer(s->spi, data_l);
+s->regs[R_PSPI_DATA] = (data_h | data_l);
Peter Maydell 於 2025年5月11日 週日 下午9:58寫道：
>
> On Sun, 11 May 2025 at 14:47, Peter Maydell wrote:
> >
> > On Wed, 7 May 2025 at 10:19, Tim Lee wrote:
> > >
> >
Philippe Mathieu-Daudé 於 2025年5月8日 週四 下午2:19寫道：
>
> Hi Tim,
>
> On 8/5/25 04:15, Tim Lee wrote:
> > Fix flash device part number to `mx66l1g45g` according image-bmc run on
> > npcm8xx
> > evb board (SPIFlash...SF: Detected mx66l1g45g, total 128 MiB)
> >
>
:
qemu-system-aarch64: mx66l1g45g device '/machine/unattached/device[73]'
requires 134217728 bytes, mtd0 block backend provides 67108864 bytes
Tested:
Build passes and runs ./qemu-system-aarch64 -machine npcm845-evb normally
Signed-off-by: Tim Lee
---
Changes since v1:
- Add a stat
- Created qtest to check initialization of registers in PSPI Module
- Implemented test into Build File
Tested:
./build/tests/qtest/npcm8xx-pspi_test
Signed-off-by: Tim Lee
---
Changes since v1:
- MAINTAINERS file not need to change
- Add comment for copyright/license information
- Correct CTL
Hi Peter,
Thanks for your suggestion. Those changes will be included in v2.
Peter Maydell 於 2025年5月6日 週二 下午8:52寫道：
>
> On Fri, 18 Apr 2025 at 10:12, Tim Lee wrote:
> >
> > - Created qtest to check initialization of registers in PSPI Module
> > - Implemented test into B
// Handle writable storage
if (blk_size < fiu->flash_size) {
blk_get_perm(blk, &perm, &shared_perm);
blk_set_perm(blk, BLK_PERM_ALL, BLK_PERM_ALL, &error_abort);
blk_truncate(blk, fiu->flash_size, true, PREALLOC_MODE_OFF,
BDRV_REQ_ZERO_WRITE, &error_abort);
blk_set_perm(blk, perm, shared_perm, &error_abort);
}
}
--
Best regards,
Tim Lee
tmp/qtest-974125.qmp,id=char0 -mon
chardev=char0,mode=control -display none -audio none -machine
npcm845-evb -accel qtest
[I 0.00] OPENED
[R +0.076480] endianness
[S +0.076506] OK little
{"QMP": {"version": {"qemu": {"micro": 50, "minor": 2, "major": 9},
"package": "v9.2.0-2138-g694a7d11fc"}, "capabilities": ["oob"]}}
{"execute": "qmp_capabilities"}
{"return": {}}
[R +0.079280] writel 0xf0201002 0x5
[S +0.079288] OK
[R +0.079312] writew 0xf0201000 0x1234
[S +0.079316] OK
Wrote 0x1234 to data register
[R +0.079337] readw 0xf0201000
[S +0.079341] OK 0x1234
Read 0x1234 from data register
[I +0.079565] CLOSED
ok 3 /aarch64/npcm8xx_pspi/data
# End of npcm8xx_pspi tests
# End of aarch64 tests
--
Best regards,
Tim Lee
to different
ARMCPUInfo which could cause some features to not be applied correctly
in specific initial functions: "cortex_a9_initfn" and
"aarch64_a35_initfn".
Sincerely,
Tim Lee
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
Correct the `valid_cpu_types` setting to match the NPCM8XX SoC.
Signed-off-by: Tim Lee
---
hw/arm/npcm8xx_boards.c | 2 +-
1 file changed, 1 insertion(+), 1
- Created qtest to check initialization of registers in PSPI Module
- Implemented test into Build File
Tested:
./build/tests/qtest/npcm8xx-pspi_test
Signed-off-by: Tim Lee
---
MAINTAINERS | 1 +
tests/qtest/meson.build | 3 +
tests/qtest/npcm8xx_pspi-test.c
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices. Attach it to the NPCM8XX.
Tested:
NPCM8XX PSPI driver probed successfully from dmesg log.
Signed-off-by: Tim Lee
---
hw/arm/npcm8xx.c | 11 ++-
include/hw/arm/npcm
:
qemu-system-aarch64: mx66l1g45g device '/machine/unattached/device[73]'
requires 134217728 bytes, mtd0 block backend provides 67108864 bytes
Tested:
Build passes and runs ./qemu-system-aarch64 -machine npcm845-evb normally
Signed-off-by: Tim Lee
---
hw/arm/npcm8xx_boa
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