, the vector offset is logically ORed with the offset
0xF000.
This means if EPH is;
* 0 - Exceptions vectors start at EVBAR
* 1 - Exception vectors start at EVBAR | 0xF000
Signed-off-by: Tim 'mithro' Ansell
---
target/openrisc/interrupt.c | 3 +++
1 file changed, 3 insertions(+
ption Vector Base Address Register (EVBAR).
Its presence is indicated by the EVBARP bit in the CPU Configuration
Register (CPUCFGR).
Signed-off-by: Tim 'mithro' Ansell
---
target/openrisc/cpu.c| 2 ++
target/openrisc/cpu.h| 7 +++
target/openrisc/interrupt.c | 6
Hi,
This patch series improves the exception vectoring on the OpenRISC platform by
adding support for both the EVBAR register and EPH bit.
This is my first patch to upstream QEMU, so please do point of if I have done
anything silly.
Tim 'mithro' Ansell (2):
target/openrisc: Imple
