[Qemu-devel] Keeping a secondary CPU in reset

Hi, I've been toying around with adding NVIDIA Tegra support to QEMU. While adding SMP support I came across a problem: on Tegra, the secondary CPU is kept in reset by the clock-and-reset controller (CRC). When bringing up the secondary CPU, the OS writes a given register in the CRC to release the

[Qemu-devel] Keeping a secondary CPU in reset

Hi, I've been toying around with adding NVIDIA Tegra support to QEMU. While adding SMP support I came across a problem: on Tegra, the secondary CPU is kept in reset by the clock-and-reset controller (CRC). When bringing up the secondary CPU, the OS writes a given register in the CRC to release the