Hello Francis,
Yes thank you. I added code to setup a basic PMP and it works now. Thank
you and best regards,
Teodori Serge
On Sun, 18 Apr 2021, 05:55 Alistair Francis, <1923...@bugs.launchpad.net>
wrote:
> We fixed a bug to make QEMU act more like hardware, which now means that
>
Hello Francis,
I'll configure PMP than do the test again. Sorry I hadn't understood what
changed between version 5.2 and 6.0-rc2, since my code worked before.
Best regards,
Teodori Serge
On Thu, 15 Apr 2021, 06:15 Alistair Francis, <1923...@bugs.launchpad.net>
wrote:
> I&#
** Changed in: qemu
Status: New => Confirmed
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https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
Confirmed
Bug description:
Public bug reported:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loo
Hello as far as I can tell, there is a major problem with PLIC
implementation. When decompiling DTB on virt board with X harts, I see
that hartid 0 has MEI and SEI, hartid 1 has MEI and SEI, etc... But when
configuring context 1 (hartid 0 SEI) no interrupt is generated, but
context 0, 2, 4 etc... w
code from machine mode:
/* TEST jump to supervisor mode */
if(mhartid == 3){
asm volatile ("csrw sepc, %[reg]; sret" : : [reg] "r"
(&main_supervisor));
log("main: jump to supervisor mode failed!\r\n");
}
here is supervisor mode function:
** Attachment added: "qemu log"
https://bugs.launchpad.net/qemu/+bug/1859291/+attachment/5324981/+files/monitor.txt
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https://bugs.launchpad.net/bugs/1859291
Title:
RISC-V incorrect
Public bug reported:
When using 'ecall' from supervisor mode, user exception is raised
instead of supervisor exception. The problem is located under
'target/riscv/insn_trans/trans_priviledged.inc.c' in function 'static
bool trans_ecall(DisasContext *ctx, arg_ecall *a)'. Best regards, Serge
Teodori
