Hi,
Any other concerns for this series?
Thanks
Suravee
On 3/4/2025 9:17 PM, Suravee Suthikulpanit wrote:
Currently, amd-iommu device does not support migration. This series addresses
an issue due hidden AMDVI-PCI device enumeration. Then introduces migratable
VMStateDescription, which saves ne
On 3/9/2025 8:44 PM, Michael S. Tsirkin wrote:
On Tue, Mar 04, 2025 at 06:37:47PM +, Suravee Suthikulpanit wrote:
The QEMU-emulated AMD IOMMU PCI device is implemented based on the AMD I/O
Virtualization Technology (IOMMU) Specification [1]. The PCI id for this
device is platform-specific
On 3/5/2025 1:52 PM, Michael S. Tsirkin wrote:
On Tue, Mar 04, 2025 at 06:37:47PM +, Suravee Suthikulpanit wrote:
The QEMU-emulated AMD IOMMU PCI device is implemented based on the AMD I/O
Virtualization Technology (IOMMU) Specification [1]. The PCI id for this
device is platform-specific
On 3/6/2025 3:58 PM, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 09:11:53AM +0200, Yan Vugenfirer wrote:
On Wed, Mar 5, 2025 at 8:54 AM Michael S. Tsirkin wrote:
On Tue, Mar 04, 2025 at 06:37:47PM +, Suravee Suthikulpanit wrote:
The QEMU-emulated AMD IOMMU PCI device is implement
On 3/5/2025 6:02 AM, Donald Dutile wrote:
Hi Suravee!
Not your issue, but wondering if others know:
Why isn't this an issue for Intel-vtd-iommu & ARM-SMMUV3 ?
Are they instantiated as non-PCI-id (platform) devices, but AMD puts
their IOMMU in PCI space?
Adv. thanks for the info.
Unlike
On 2/21/2025 7:38 AM, Michael S. Tsirkin wrote:
On Wed, Feb 12, 2025 at 05:44:49AM +, Suravee Suthikulpanit wrote:
Current amd-iommu model internally creates an AMDVI-PCI device. Here is
a snippet from info qtree:
bus: main-system-bus
type System
dev: amd-iommu, id ""
Daniel,
On 2/6/2025 4:01 PM, Daniel P. Berrangé wrote:
On Thu, Feb 06, 2025 at 05:18:56AM +, Suravee Suthikulpanit wrote:
Add migration support for AMD IOMMU model by saving necessary AMDVIState
parameters for MMIO registers, device table, command buffer, and event
buffers.
Signed-off-by:
On 11/29/2024 12:14 AM, Joao Martins wrote:
On 21/11/2024 11:42, Joao Martins wrote:> On 20/11/2024 07:31, Suravee
Suthikulpanit wrote:
Add migration support for AMD IOMMU model by saving necessary AMDVIState
parameters for MMIO registers, device table, command buffer, and event
buffers.
Sig
On 11/21/2024 6:42 PM, Joao Martins wrote:
On 20/11/2024 07:31, Suravee Suthikulpanit wrote:
Add migration support for AMD IOMMU model by saving necessary AMDVIState
parameters for MMIO registers, device table, command buffer, and event
buffers.
Signed-off-by: Suravee Suthikulpanit
---
hw/
On 6/8/2023 3:40 PM, Igor Mammedov wrote:
On Wed, 7 Jun 2023 15:57:16 -0500
Suravee Suthikulpanit wrote:
Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
(32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
supported since QEMU 7.0, default to
On 6/7/2023 3:11 PM, Daniel P. Berrangé wrote:
On Tue, Jun 06, 2023 at 09:49:37PM -0500, Suravee Suthikulpanit wrote:
Into a helper function pc_machine_init_smbios() in preparation for
subsequent code to upgrade default SMBIOS entry point type.
Then, call the helper function from the pc_mach
On 6/7/2023 8:49 PM, Igor Mammedov wrote:
On Tue, 6 Jun 2023 21:49:38 -0500
Suravee Suthikulpanit wrote:
and use this with the rest of your patch
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index b3d826a83a..c5bab28e9c 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1859,7 +1859,7 @@ st
Igor,
On 6/6/2023 3:11 PM, Igor Mammedov wrote:
On Tue, 6 Jun 2023 09:35:41 +0200
Igor Mammedov wrote:
On Mon, 5 Jun 2023 16:39:05 -0500
Suravee Suthikulpanit wrote:
[...]
+/* For pc-i44fx-8.0 and older, use SMBIOS 2.8 by default */
+pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POIN
On 6/6/2023 2:35 PM, Igor Mammedov wrote:
On Mon, 5 Jun 2023 16:39:05 -0500
Suravee Suthikulpanit wrote:
Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
(32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
supported since QEMU 7.0, default to
Igor,
On 6/6/2023 2:55 PM, Igor Mammedov wrote:
On Mon, 5 Jun 2023 16:39:06 -0500
Suravee Suthikulpanit wrote:
Since KVM_MAX_VCPUS is currently defined to 1024 for x86 as shown in
arch/x86/include/asm/kvm_host.h, update QEMU limits to the same number.
In case KVM could not support the specif
Igore,
On 6/6/2023 2:45 PM, Igor Mammedov wrote:
On Mon, 5 Jun 2023 16:39:04 -0500
Suravee Suthikulpanit wrote:
In preparation for subsequent code to upgrade default SMBIOS
entry point type. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
hw/i386/pc.c | 12
Michael,
On 6/4/2023 7:55 PM, Michael S. Tsirkin wrote:
On Fri, Jun 02, 2023 at 10:22:54PM -0500, Suravee Suthikulpanit wrote:
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -199,6 +199,14 @@ static void pc_q35_init(MachineState *machine)
pc_guest_info_init(pcms);
if (pcm
On 6/1/2023 6:09 PM, Michael S. Tsirkin wrote:
On Thu, Jun 01, 2023 at 11:17:30AM +0100, Daniel P. Berrangé wrote:
On Thu, Jun 01, 2023 at 11:09:45AM +0100, Joao Martins wrote:
On 31/05/2023 23:51, Suravee Suthikulpanit wrote:
Since KVM_MAX_VCPUS is currently defined to 1024 for x86 as sho
Hi All,
Currently, we don't have a good way to check whether APICV is active on a VM.
Normally, For AMD SVM AVIC, users either have to check for trace point, or using
"perf kvm stat live" to catch AVIC-related #VMEXIT.
For KVM, I would like to propose introducing a new IOCTL interface (i.e.
KVM
Igor,
On 5/9/2022 2:12 PM, Igor Mammedov wrote:
On Wed, 4 May 2022 08:16:39 -0500
Suravee Suthikulpanit wrote:
This is the maximum number of vCPU supported by
the AMD x2APIC virtualization.
Signed-off-by: Suravee Suthikulpanit
---
hw/i386/pc_q35.c | 2 +-
1 file changed, 1 insertion(+), 1
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