..@linaro.org> wrote:
> On 1/6/22 1:14 AM, Stevie Lavern wrote:
> > Do you think it qualifies as "trivial patch" or should i go on with the
> full patch
> > submission process?
>
> There is no "short" patch submission process.
>
>
> r~
>
The AVX instruction set is not supported by Qemu.
However, some AVX instructions are properly decoded and emulated as their
legacy SSE version.
This patch prevent this by generating an illegal_op instead of a bogus SSE
instruction.
Signed-off-by: Stevie Lavern
---
target/i386/tcg/translate.c
chard Henderson <
richard.hender...@linaro.org> wrote:
> On 1/5/22 9:09 AM, Stevie Lavern wrote:
> > Hello,
> > I'm currently testing various binaries under qemu linux user and went
> into a strange bug.
> >
> > Here is the TLDR: is there a reason to allow VEX.L to be
Hello,
I'm currently testing various binaries under qemu linux user and went into
a strange bug.
Here is the TLDR: is there a reason to allow VEX.L to be 1 when not
supporting AVX instructions? Crashing with illegal op may save some time
and headache to users.
And now for some context:
One of my
my case, after loop reentry, it led to an invalid branch to be taken.
Thanks for your time!
Regards
Stevie
On Thu, Aug 5, 2021 at 1:33 PM Paolo Bonzini wrote:
> On 05/08/21 13:24, Paolo Bonzini wrote:
> > On 05/08/21 11:51, Stevie Lavern wrote:
> >>
> >> S
Hello,
I'm posting this here instead of opening an issue as it is not clear to me
if this is a bug or not.
The issue is located in function "cpu_compute_eflags" in target/i386/cpu.h
(https://gitlab.com/qemu-project/qemu/-/blob/master/target/i386/cpu.h#L2071)
This function is exectued in an out o
Hi,
I also noticed that the 4.2.0 release changelog mentions support for
some AVX512 instructions.
https://wiki.qemu.org/ChangeLog/4.2#x86
```
Support for AVX512 BFloat16 extensions.
```
Is this support in TCG or in another component?
If so, it would mean that TCG support some AVX512 instruction
Thanks for your answers.
I thought the fact that there was not any warning/exception meant that
VMOVDQU was supported, but if it's mistakenly interpreted as MOVDQU then
I understand.
I read the mailing list messages on the AVX GSoC you point out, but
couldn't find any branch where this work is lo
Public bug reported:
Hi,
Tested with Qemu 4.2.0, and with git version
bddff6f6787c916b0e9d63ef9e4d442114257739.
The x86 AVX instruction VMOVDQU doesn't work properly with YMM registers (32
bytes).
It works with XMM registers (16 bytes) though.
See the attached test case `ymm.c`: when copying f
Note: Qemu has been built with the following commands:
```
% ./configure --target-list=x86_64-linux-user && make
OR
% ./configure --target-list=x86_64-linux-user --enable-avx2 && make
```
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