On Tue, Jan 07, 2025 at 05:56:52AM -0600, Rob Landley wrote:
> On 12/31/24 19:19, Rob Landley wrote:
> > On 12/23/24 07:05, Stafford Horne wrote:
> > > > The kernel config looks like it should have virt block device
> > > > support, but
> ...
> > >
On Thu, Dec 19, 2024 at 08:08:14PM +, Joel Holdsworth wrote:
> > > > > +/* Zero the count by applying a negative offset to the
> > > > > counter */
> > > > > +or1k_timer->ttcr_offset += UINT32_MAX - (cpu->env.ttmr &
> > > > > TTMR_TP);
> > > >
> > > > Since UINT32_MAX is -1 in
, but without
accumulating error over time.
Signed-off-by: Joel Holdsworth
[stafford: Incremented version in vmstate_or1k_timer, checkpatch fixes]
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff
a468 ("hw/openrisc: support 4 serial ports in or1ksim")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ahmad Fatoum
[stafford: Change to serial0 alias and update change message, reverse
uart registration order]
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
---
hw/openrisc/openris
The following changes since commit f0a5a31c33a8109061c2493e475c8a2f4d022432:
Update version for v9.2.0-rc0 release (2024-11-13 21:44:45 +)
are available in the Git repository at:
https://github.com/stffrdhrn/qemu.git tags/pull-or1k-20241203
for you to fetch changes up to 3eb43aeb164f1f8
, but without
accumulating error over time.
Signed-off-by: Joel Holdsworth
[stafford: Incremented version in vmstate_or1k_timer, checkpatch fixes]
Signed-off-by: Stafford Horne
---
Since v2:
- Nothing
Since v1:
- Use DIVIDE_ROUND_UP instead of open coding as pointed out by Richard
- Fix off-by
a468 ("hw/openrisc: support 4 serial ports in or1ksim")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Ahmad Fatoum
[stafford: Change to serial0 alias and update change message, reverse
uart registration order]
Signed-off-by: Stafford Horne
Reviewed-by: Peter Maydell
---
Since v2:
- Fruther
This series has 2 fixes for OpenRISC that came in over that past few months.
Since v2:
- Update the commit message of the serial@9000 patch to indicate the
changes from v2.
Since v1:
- Use DIVIDE_ROUND_UP instead of open coding as pointed out by Richard
- Fix off-by-1 bug in TTCR patch p
On Mon, Dec 02, 2024 at 04:54:11PM +, Peter Maydell wrote:
> On Sun, 1 Dec 2024 at 07:11, Stafford Horne wrote:
> >
> > This series has 2 fixes for OpenRISC that came in over that past few months.
> >
> > Since v1:
> > - Use DIVIDE_ROUND_UP instead of open
y: Ahmad Fatoum
[stafford: Change to serial0 alias and update change message, reverse
uart registration order]
Signed-off-by: Stafford Horne
---
Since v1:
- Fix commit message and reverse registration order as pointed out by Peter.
hw/openrisc/openrisc_sim.c | 26 --
1 file
This series has 2 fixes for OpenRISC that came in over that past few months.
Since v1:
- Use DIVIDE_ROUND_UP instead of open coding as pointed out by Richard
- Fix off-by-1 bug in TTCR patch pointed out by Richard
- Fix commit message and reverse registration order as pointed out by Peter.
Ahm
, but without
accumulating error over time.
Signed-off-by: Joel Holdsworth
[stafford: Incremented version in vmstate_or1k_timer, checkpatch fixes]
Signed-off-by: Stafford Horne
---
Since v1:
- Use DIVIDE_ROUND_UP instead of open coding as pointed out by Richard
- Fix off-by-1 bug in TTCR patch
On Sun, Dec 01, 2024 at 06:44:39AM +, Stafford Horne wrote:
> On Mon, Nov 25, 2024 at 02:02:35PM +, Peter Maydell wrote:
> > On Sat, 23 Nov 2024 at 10:39, Stafford Horne wrote:
> > >
> > > From: Ahmad Fatoum
> > >
> > > We used to only
On Mon, Nov 25, 2024 at 02:02:35PM +, Peter Maydell wrote:
> On Sat, 23 Nov 2024 at 10:39, Stafford Horne wrote:
> >
> > From: Ahmad Fatoum
> >
> > We used to only have a single UART on the platform and it was located at
> > address 0x9000. When the n
On Sun, Nov 24, 2024 at 08:03:53AM +0300, Michael Tokarev wrote:
> 23.11.2024 20:01, Stafford Horne wrote:
> > On Sat, Nov 23, 2024 at 03:12:12PM +0300, Michael Tokarev wrote:
> > > On 23.11.2024 13:38, Stafford Horne wrote:
> > > > This series has 2 fixes for OpenRI
On Sat, Nov 23, 2024 at 11:18:53PM -0600, Rob Landley wrote:
...
> I'm attempting to regression test as many targets as I can to get consistent
> basic behavior out of:
>
> https://landley.net/bin/mkroot/0.8.11/
>
> I'm trying to get a new release out with the 6.12 kernel which is why I'm
> rev
On Sat, Nov 23, 2024 at 07:39:57AM -0600, Richard Henderson wrote:
> On 11/23/24 04:38, Stafford Horne wrote:
> > +or1k_timer->ttcr = or1k_timer->ttcr_offset +
> > +(now - or1k_timer->clk_offset + TIMER_PERIOD - 1) / TIMER_PERIOD;
>
> Better using DIV_RO
On Sat, Nov 23, 2024 at 03:12:12PM +0300, Michael Tokarev wrote:
> On 23.11.2024 13:38, Stafford Horne wrote:
> > This series has 2 fixes for OpenRISC that came in over that past few months.
> >
> > Ahmad Fatoum (1):
> >hw/openrisc/openrisc_sim: keep serial@90
, but without
accumulating error over time.
Signed-off-by: Joel Holdsworth
[stafford: Incremented version in vmstate_or1k_timer, checkpatch fixes]
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff
This series has 2 fixes for OpenRISC that came in over that past few months.
Ahmad Fatoum (1):
hw/openrisc/openrisc_sim: keep serial@9000 as default
Joel Holdsworth (1):
hw/openrisc: Fixed undercounting of TTCR in continuous mode
hw/openrisc/cputimer.c | 26 +++--
ange to serial0 alias and update change message]
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 9fb63515ef..5ec9172ccf 100644
--- a/hw/o
On Fri, Nov 22, 2024 at 06:54:21PM -0600, Rob Landley wrote:
> On 11/22/24 10:35, Stafford Horne wrote:
> > > I just regression tested linux-6.12 against qemu-9.2.0-rc1 and I'm still
> > > getting no output from or1k, with the current image or the old or1k
> > &
On Thu, Nov 21, 2024 at 04:32:25PM -0600, Rob Landley wrote:
> On 9/16/24 02:21, Stafford Horne wrote:
> > On Wed, Sep 11, 2024 at 12:42:58AM -0500, Rob Landley wrote:
> > > Grab this tarball, extract it, and ./run-qemu.sh. It's a simple
> > > linux+initramfs im
On Fri, Jun 07, 2024 at 03:29:33PM -0700, Joel Holdsworth via wrote:
> In the existing design, TTCR is prone to undercounting when running in
> continuous mode. This manifests as a timer interrupt appearing to
> trigger a few cycles prior to the deadline set in SPR_TTMR_TP.
>
> When the timer trig
Hi Rob,
Sorry, I haven't had much time to sit down and work on this mail in the last two
weeks but wanted to get somethign back to you. Here it goes.
On Wed, Sep 11, 2024 at 12:42:58AM -0500, Rob Landley wrote:
> Grab this tarball, extract it, and ./run-qemu.sh. It's a simple
> linux+initramfs i
ange to serial0 alias and update change message]
Signed-off-by: Stafford Horne
---
Since v1:
- Stafford is sending the patch for Ahmad now.
- Added 'Fixes'
- Only define stdout-path one time.
- Change alias name from 'uartN' to 'serialN'
hw/openrisc/openrisc_sim.c
On Wed, Aug 28, 2024 at 04:38:49PM +0100, Peter Maydell wrote:
> On Tue, 27 Aug 2024 at 19:53, Stafford Horne wrote:
> >
> > On Sun, Aug 25, 2024 at 03:09:20PM +0100, Peter Maydell wrote:
> > > On Sun, 25 Aug 2024 at 12:35, Jason A. Donenfeld wrote:
> > > >
&
On Sun, Aug 25, 2024 at 03:09:20PM +0100, Peter Maydell wrote:
> On Sun, 25 Aug 2024 at 12:35, Jason A. Donenfeld wrote:
> >
> > On Fri, Aug 23, 2024 at 07:28:43AM +0100, Stafford Horne wrote:
> > > Also, I will wait to see if Jason has anything to say.
> >
> >
On Fri, Aug 23, 2024 at 09:23:23AM +0200, Ahmad Fatoum wrote:
> Hello Stafford,
>
> On 23.08.24 08:28, Stafford Horne wrote:
> > Note the distribution list you use here: openr...@lists.librecores.org
> > Is old and we should use linux-openr...@vger.kernel.org. I w
Note the distribution list you use here: openr...@lists.librecores.org
Is old and we should use linux-openr...@vger.kernel.org. I will get the qemu
maintainer file updated.
On Thu, Aug 22, 2024 at 06:38:38PM +0200, Ahmad Fatoum wrote:
> We used to only have a single UART on the platform and it wa
On Mon, Jun 10, 2024 at 07:29:15PM +, Joel Holdsworth wrote:
> Hi Stafford, thanks for your response.
>
> > - You sent this 2 times, is the only change in v2 the sender address?
>
> Yes, I was just having some difficulty with Git and SMTP. Should be fixed now.
OK.
> >> In the existing desig
Hi Joel,
I am away and wont be able to have too much time to look at this.
But have a few comments below and questions.
- You sent this 2 times, is the only change in v2 the sender address?
On Fri, Jun 07, 2024 at 03:29:33PM -0700, Joel Holdsworth via wrote:
> In the existing design, TTCR is p
On Thu, Aug 10, 2023 at 09:35:18AM +0300, Michael Tokarev wrote:
> 09.08.2023 23:34, Stafford Horne пишет:
> > The architecture specification calls for the EPCR to be set to "Address
> > of next not executed instruction" when there is a floating point
> > exception
exception address when handling floating
point exceptions.
----
Stafford Horne (1):
target/openrisc: Set EPCR to next PC on FPE exceptions
target/openrisc/interrupt.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
x I used the following:
float fpu_div(float a, float b) {
float c;
asm volatile("lf.div.s %0, %1, %2"
: "+r" (c)
: "r" (a), "r" (b));
return c;
}
Reviewed-by: Richard Henderson
Signe
x I used the following:
float fpu_div(float a, float b) {
float c;
asm volatile("lf.div.s %0, %1, %2"
: "+r" (c)
: "r" (a), "r" (b));
return c;
}
Reviewed-by: Richard Henderson
Signe
On Sun, Jul 30, 2023 at 10:43:45AM -0700, Richard Henderson wrote:
> On 7/29/23 14:08, Stafford Horne wrote:
> > The architecture specification calls for the EPCR to be set to "Address
> > of next not executed instruction" when there is a floating point
> > excep
On Sat, Jul 29, 2023 at 10:08:51PM +0100, Stafford Horne wrote:
> The architecture specification calls for the EPCR to be set to "Address
> of next not executed instruction" when there is a floating point
> exception (FPE). This was not being done, so fix it by using the same
x I used the following:
float fpu_div(float a, float b) {
float c;
asm volatile("lf.div.s %0, %1, %2"
: "+r" (c)
: "r" (a), "r" (b));
return c;
}
Signed-off-by: Stafford Horne
---
target/
architecture spec updates:
- Allow FPCSR to be accessed in user mode
- Select tininess detection before rounding
- Fix FPE Exception PC value
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 0ce4f796fa
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
Reviewed-by
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/fpu_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/fpu_helper.c b/target
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
Since v2:
- Add reviewed-by
Since v1:
- Remove setting default NaN behavior.
target/openrisc/cpu.c | 4
1 file changed, 4 insertions
math tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc: Set PC to cpu state on FPU exception
target/openrisc: Setup FPU for detecting tininess before rounding
target/openrisc/cpu.c| 4 ++
target/openrisc/fpu_helper.c
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
Reviewed-by
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
Since v2:
- Add reviewed-by
Since v1:
- Use function do_fpe (similar to do_range) to raise exception.
target/openrisc/fpu_helper.c | 13
On Wed, May 10, 2023 at 05:16:20PM +0100, Richard Henderson wrote:
> On 5/10/23 16:32, Stafford Horne wrote:
> > OpenRISC defines tininess to be detected before rounding. Setup qemu to
> > obey this.
> >
> > Signed-off-by: Stafford Horne
> > ---
> > Since
On Wed, May 10, 2023 at 05:13:03PM +0100, Richard Henderson wrote:
> On 5/10/23 16:32, Stafford Horne wrote:
> > void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong
> > rb)
> > {
> > -#ifndef CONFIG_USER_ONLY
> > OpenRISCCPU *cpu
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
---
Since v1:
- Remove setting default NaN behavior. I discussed with the FPU developers and
they mentioned the OpenRISC hardware should be IEEE compliant when handling
and
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
---
Since v1:
- Use function do_fpe (similar to do_range) to raise exception.
target/openrisc/fpu_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff
as no-ops as the cpu implementations do. As mentioned
series changes FPCSR read/write to follow the spec.
The series has been tested with the FPU support added in glibc test suite and
all math tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
---
Since v1
risc
> + ~ (/qemu)?((/include)?/hw/openrisc/.*|/target/openrisc/.*)
This looks good to me for OpenRISC. Where can we view the coverity reports?
Is it this?: https://scan.coverity.com/projects/378
Acked-by: Stafford Horne
> +xtensa
> + ~ (/qemu)?((/include)?/hw/xtensa/.*|/target/xtensa/.*)
On Wed, May 03, 2023 at 10:41:42AM +0100, Richard Henderson wrote:
> On 5/3/23 10:14, Stafford Horne wrote:
> > > > +set_default_nan_mode(1, &cpu->env.fp_status);
> > > > +set_float_detect_tininess(float_tininess_before_rounding,
> > > > +
On Wed, May 03, 2023 at 08:37:31AM +0100, Richard Henderson wrote:
> On 5/2/23 19:57, Stafford Horne wrote:
> > OpenRISC defines tininess to be detected before rounding. Setup qemu to
> > obey this.
> >
> > Signed-off-by: Stafford Horne
> > ---
> > targe
On Wed, May 03, 2023 at 08:36:13AM +0100, Richard Henderson wrote:
> On 5/2/23 19:57, Stafford Horne wrote:
> > @@ -55,6 +56,9 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
> > if (tmp) {
> > env->fpcsr |= tmp;
> >
On Tue, May 02, 2023 at 07:57:29PM +0100, Stafford Horne wrote:
> As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
>
> Update mtspr and mfspr helpers to support this by moving the is_user
> check into the helper.
>
> There is a logic change here to no longe
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
---
target/openrisc/fpu_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index f9e34fa2cc..1feebb9ac7 100644
instruction exception is not part of the spec, so this should be OK.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
---
target/openrisc/sys_helper.c | 45 +-
target/openrisc/translate.c | 72
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
---
target/openrisc/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 0ce4f796fa..cdbff26fb5 100644
--- a/target
mentioned
series changes FPCSR read/write to follow the spec.
The series has been tested with the FPU support added in glibc test suite and
all math tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc: Set PC to cpu state on FPU exception
target
has been
> added, so that we have a pointer to that copy of the FDT.
This looks good to me.
Acked-by: Stafford Horne
> Cc: Stafford Horne
> Signed-off-by: Jason A. Donenfeld
> ---
> hw/openrisc/boot.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/ope
: Stafford Horne
---
target/openrisc/cpu.c| 1 -
target/openrisc/sys_helper.c | 7 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 41d1b2a24a..cb9f35f408 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -98,7
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
docs/system/openrisc/cpu-features.rst | 15 ++
docs/system/openrisc/emulation.rst| 17 +++
docs/system/openrisc/or1k-sim.rst | 43
docs/system/openrisc/virt.rst | 50
When we are tracing it's helpful to know which CPU's are getting
interrupted, add that detail to the log line.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/targe
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne
---
hw/openrisc/Kconfig | 3 +
hw/openrisc/virt.c | 160
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
configs/targets/or1k-softmmu.mak | 1 +
target/openrisc
C SMP with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne
---
configs/devices/or1k-softmmu/default.mak |
. Global cpu timer (last_clk and ttcr) reset, attached to the first
cpu only.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc
These will be shared with the virt platform.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/boot.c | 116 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106 ++---
include
Donenfeld
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/virt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index 9a78234a28..f8a68a6a6b 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt.c
@@ -8,6 +8,7 @@
#inc
ent Vivier
Reviewed-by: Anup Patel
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/m68k/virt.c| 1 +
hw/rtc/goldfish_rtc.c | 37 ++-
include/hw/rtc/goldfish_rtc.h | 2 ++
3 files changed, 31 insertions(+), 9 deletion
protection mapping then falling back to PAGE_EXEC.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
target/openrisc/mmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index d7e1320998..0b8afdbacf 100644
--
Highlights
include:
- New virt plaform with, virtio and pci bus support
- OpenRISC support for MTTCG
- Goldfish RTC device endianness is configurable now
Jason A. Donenfeld (1):
hw/openrisc: virt: pass random seed to fdt
Stafford
On Fri, Jul 29, 2022 at 04:42:54PM -0700, Richard Henderson wrote:
> On 7/29/22 16:01, Stafford Horne wrote:
> > This patch enables multithread TCG for OpenRISC. Since the or1k shared
> > syncrhonized timer can be updated from each vCPU via helpers we use a
> > mutex t
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2;
- Added Reviewed-by
docs/system/openrisc/cpu-features.rst | 15 ++
docs/system/openrisc/emulation.rst| 17 +++
docs/system/openrisc/or1k-sim.rst | 43
docs/system/openrisc/virt.rst
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne
---
Since v2:
- Removed cpu_openrisc_timer_has_advanced lock optimization, measuring revealed
ent Vivier
Reviewed-by: Anup Patel
Signed-off-by: Stafford Horne
---
Since v2:
- Added Reviewed-by
- Changed from enum property to boolean as suggested by Richard
hw/m68k/virt.c| 1 +
hw/rtc/goldfish_rtc.c | 37 ++-
include/hw/rtc/gold
Donenfeld
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
hw/openrisc/virt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index 9a78234a28..f8a68a6a6b 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt
When we are tracing it's helpful to know which CPU's are getting
interrupted, add that detail to the log line.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- Added Reviewed-by
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+),
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
hw/openrisc/Kconfig | 3 +
hw
protection mapping then falling back to PAGE_EXEC.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- No changes, added Reviewed-by
target/openrisc/mmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/m
These will be shared with the virt platform.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
hw/openrisc/boot.c | 117 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106
: Stafford Horne
---
Since v2:
- Added Reviewed-by
target/openrisc/cpu.c| 1 -
target/openrisc/sys_helper.c | 7 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 41d1b2a24a..cb9f35f408 100644
--- a/target/openrisc/cpu.c
. Global cpu timer (last_clk and ttcr) reset, attached to the first
cpu only.
Signed-off-by: Stafford Horne
---
Since v2:
- Moved timer init from init to reset suggested by Richard
hw/openrisc/cputimer.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git
C SMP with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
configs/devices/or
andom seed to fdt
Stafford Horne (10):
hw/openrisc: Split re-usable boot time apis out to boot.c
target/openrisc: Fix memory reading in debugger
goldfish_rtc: Add big-endian property
hw/openrisc: Add the OpenRISC virtual machine
hw/openrisc: Add PCI bus support to virt
hw/openrisc: Initi
On Mon, Jul 04, 2022 at 12:23:23PM +0200, Laurent Vivier wrote:
> On 04/07/2022 12:21, Richard Henderson wrote:
> > On 7/4/22 15:46, Laurent Vivier wrote:
> > > On 04/07/2022 11:59, Richard Henderson wrote:
> > > > On 7/4/22 02:58, Stafford Horne wrote:
> >
On Mon, Jul 04, 2022 at 03:29:57PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > -static const MemoryRegionOps goldfish_rtc_ops = {
> > -.read = goldfish_rtc_read,
> > -.write = goldfish_rtc_write,
> > -.endianness = DEVICE_NAT
On Mon, Jul 04, 2022 at 03:33:26PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > The last_clk time was initialized at zero, this means when we calculate
> > the first delta we will calculate 0 vs current time which could cause
>
On Mon, Jul 04, 2022 at 03:37:04PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > case TO_SPR(10, 1): /* TTCR */
> > -cpu_openrisc_count_update(cpu);
> > +if (cpu_openrisc_timer_has_advanced(cpu)) {
> > +
On Mon, Jul 04, 2022 at 03:34:52PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > When we are tracing it's helpful to know which CPU's are getting
> > interrupted, att that detail to the log line.
>
> "at".
>
> Reviewe
Signed-off-by: Stafford Horne
---
docs/system/openrisc/cpu-features.rst | 15 ++
docs/system/openrisc/emulation.rst| 17 +++
docs/system/openrisc/or1k-sim.rst | 43
docs/system/openrisc/virt.rst | 50 +++
docs/system/target-openrisc.rst
From: "Jason A. Donenfeld"
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Stafford Horne
Signed-off
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne
---
configs/targets/or1k-softmmu.mak | 1 +
hw/openrisc/cputimer.c | 17
not correct as masked interrupts
should still be visible in PICSR.
2. After setting PICMR (mask register) and exposed interrupts should
cause an interrupt to be raised. This was not being done so add it.
This patch fixes both issues.
Signed-off-by: Stafford Horne
---
target/openrisc
C SMP with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne
---
configs/devices/or1k-softmmu/default.mak |
The last_clk time was initialized at zero, this means when we calculate
the first delta we will calculate 0 vs current time which could cause
unnecessary hops.
Initialize last_clk to the qemu clock on initialization.
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 1 +
1 file
When we are tracing it's helpful to know which CPU's are getting
interrupted, att that detail to the log line.
Signed-off-by: Stafford Horne
---
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/interrupt.c b/targe
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