'mcrxr' instruction
was assuming that the flags are stored in bit 2, and was shifting them
right (incorrectly)
Signed-off-by: Sorav Bansal
---
target-ppc/translate.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/transla
> Your patch is missing the signoff.
Here is the patch with the signoff. thanks.
>From da0a962a6d14fe699ebb7cc12450c7de9553b66a Mon Sep 17 00:00:00 2001
From: Sorav Bansal
Date: Wed, 11 Jun 2014 19:49:49 +0530
Subject: [PATCH] Fixed the translation of the mcrxr ppc instruction
---
targ
spec starts bit numbering at the MSB. Here is
the revised patch.
>From da0a962a6d14fe699ebb7cc12450c7de9553b66a Mon Sep 17 00:00:00 2001
From: Sorav Bansal
Date: Wed, 11 Jun 2014 19:49:49 +0530
Subject: [PATCH] Fixed the translation of the mcrxr ppc instruction
---
target-ppc/translate.c |
generate the final
XER value. The old code seemed to be assuming that the flags are
stored in bit 2, and was shifting them right (by their respective
offsets), which seems incorrect.
>From 31f39e258cbb289c2e0a3c3adde87cde7ae02a15 Mon Sep 17 00:00:00 2001
From: Sorav Bansal
Date: Tue, 10 Jun 2014
Dear qemu-devs,
Two questions about what seems to be a deviation in the qemu-implementation
from PowerPC specification:
1. In comparison operations (eg. PPC_OP(cmp)), why does qemu not set the SO
bit (which will be the fourth bit) of T0? The spec says that the xer_so bit
is copied into the fourt
I want to instrument call instruction so that my
tracking function is called on each call instruction.
>From what I understand, I should
a) change target-i386/translate.c case 0xe8 to
generate my own microinstruction, say gen_op_mycall()
b) Add functionality of op_mycall() to
target-i386/op.c
c)
