when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
target/loongarch/cpu.c | 10 +-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch
Implement avec set irq and update CSR_MSIS.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index 1f9f376898..af6c75c4a9 100644
--- a
implement the read-clear feature for CSR_MSGIR register.
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 21 +++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 24
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1
when cpu added, connect avec irq to cpu INT_AVEC irq pin.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 71
hw/loongarch/virt.c | 11 +++
2 files changed, 82 insertions(+)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 27 +--
3 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/target
move some machine define to virt.h
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
include/hw/loongarch/virt.h | 19 +++
target/loongarch/cpu.h | 21 -
2 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/include/hw/loongarch/virt.h b
into one patch8;
4: Fix patch7 get wrong cpu_num and irq_num;
5: Add vmstate_msg for messag-interrupt registers migrate;
6: Update test scripts use '-bios', because kernel use avec need acpi
support. the bios is qemu/pc_bios/edk2-loongarch64-code.fd.bz2.
Thanks.
Song Gao
Song G
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 20
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3 files changed, 31 insertions(+), 3 deletions
default avec feature bit.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 30 ++
include/hw/loongarch/virt.h | 14 ++
2 files changed, 44 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index b15ada2078..112cf9a9db 100644
--- a
Add feature register and misc register for avecintc feature checking and
setting
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 112cf9a9db..0d05404eb5 100644
--- a/hw/loongarch
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 20
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3 files changed, 31 insertions(+), 3 deletions
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 27 +--
3 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/target
Add write misc avecintc status bit and read avecintc feature and status bit.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 112cf9a9db..26db1bbd68 100644
--- a/hw/loongarch/virt.c
-off-by: Song Gao
---
hw/loongarch/virt.c | 30 ++
include/hw/loongarch/virt.h | 13 +
2 files changed, 43 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index b15ada2078..112cf9a9db 100644
--- a/hw/loongarch/virt.c
+++ b/hw
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1
implement the read-clear feature for CSR_MSGIR register.
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 22 +++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans
me code style;
3: Merge patch8 and patch9 into one patch8;
4: Fix patch7 get wrong cpu_num and irq_num;
5: Add vmstate_msg for messag-interrupt registers migrate;
6: Update test scripts use '-bios', because kernel use avec need acpi
support. the bios is qemu/pc_bios/edk2-loongarch
when cpu added, connect avec irq to cpu INT_AVEC irq pin.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 71
hw/loongarch/virt.c | 7
2 files changed, 78 insertions(+)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
and CSR_ECFG.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
target/loongarch/cpu.c | 10 ++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 24
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1
Implement avec set irq and update CSR_MSIS.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index 1f9f376898..8ccd6092e6 100644
--- a
move some machine define to virt.h
Signed-off-by: Song Gao
---
include/hw/loongarch/virt.h | 19 +++
target/loongarch/cpu.h | 21 -
2 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
and CSR_ECFG.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
target/loongarch/cpu.c | 10 ++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu
qemu/pc_bios/edk2-loongarch64-code.fd.bz2.
v2:
1: Use one irqline for avec parent_irq;
2; Correct avec memroy area;
3; Pch-msi not connecet to avec when avec is enabled and drop patch 7;
4: Add misc_feature and misc_status for misc features an misc
Thanks.
Song Gao
Song Gao (9):
hw/loongarch
Implement avec set irq and update CSR_MSIS and CSR_MSGIR.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 44 ++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index c686ac9483
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.c | 7 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 25 +++--
4 files changed, 43 insertions(+), 2
implement the read-clear feature for CSR_MSGIR register.
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 21 +++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans
]:https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loongarch-avec.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 4
include/hw/loongarch/virt.h | 20
target/loongarch/cpu.h | 21 -
3 files changed, 24 insertions
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 24
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 21 +
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3 files changed, 32 insertions(+), 3 deletions
.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 43 +
include/hw/loongarch/virt.h | 15 +
2 files changed, 54 insertions(+), 4 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 6a169d4824..426eaaef84 100644
--- a/hw
used to notify kvm to reload register
state.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-11-maob...@loongson.cn>
Signed-off-by: Song Gao
---
hw/intc/loongarch_extioi.c | 4
hw/intc/loongarch_extioi_kvm.c | 4
hw/intc/loongarch_ipi.c
From: Bibo Mao
Add save and store funtction if kvm_irqchip_in_kernel() return true,
it is to get and set PCH PCI irqchip state from KVM kernel.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-9-maob...@loongson.cn>
Signed-off-by: Song Gao
---
h
From: Bibo Mao
Option kernel_irqchip=split is not supported on LoongArch virt machine,
report error and exit if detect split kernel_irqchip option.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063431.2557468-1-maob...@loongson.cn>
Signed-off-by: Song Gao
---
From: Bibo Mao
Function kvm_extioi_realize() is added if kvm_irqchip_in_kernel is
set. It is to create and initialize ExtIOI device in kernel mode.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-2-maob...@loongson.cn>
Signed-off-by: Song Gao
---
h
From: Bibo Mao
Add save and store funtction if kvm_irqchip_in_kernel() return true,
it is to get and set IPI irqchip state from KVM kernel.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-6-maob...@loongson.cn>
Signed-off-by: Song Gao
---
h
From: Bibo Mao
Function kvm_ipi_realize() is added if kvm_irqchip_in_kernel() return true.
It is to create and initialize IPI device in kernel mode.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-4-maob...@loongson.cn>
Signed-off-by: Song Gao
---
h
From: Bibo Mao
Register IOCSR MISC_FUNC_REG is to enable features about EXTIOI
irqchip. If EXTIOI is emulated in kernel, MISC_FUNC_REG register
should be emulated in kernel also.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063523.2557513-1-maob...@loongson.cn>
From: Bibo Mao
If kvm_irqchip_in_kernel() return true, MSI interrupt can be injected
with API kvm_irqchip_send_msi() to KVM.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-7-maob...@loongson.cn>
Signed-off-by: Song Gao
---
hw/intc/loongarch_pch_msi.
/3A5000 we got a "Illegal instruction" error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2971
Fixes: 29bb5d727ff ("target/loongarch: Implement vldi")
Cc: qemu-sta...@nongnu.org
Reviewed-by: Bibo Mao
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
From: Bibo Mao
If kvm_irqchip_in_kernel() return true, irq line interrupt can be
injected with API kvm_set_irq() to KVM.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-10-maob...@loongson.cn>
Signed-off-by: Song Gao
---
hw/intc/loongarch_pch_pic
From: Bibo Mao
Function kvm_pic_realize() is added if kvm_irqchip_in_kernel() return true.
It is to notify KVM kernel to create and initialize PCH PCI device in
kernel mode.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-8-maob...@loongson.cn>
Signed-
From: Bibo Mao
Add pre_save and post_load interfaces with ipi_common class, here only
framework ipi_common adds these interfaces. The defailed implementation
is LoongArchIPI child device in later.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-5-m
Add kernel irqchip support
Song Gao (1):
target/loongarch: fix vldi/xvldi raise wrong error
hw/intc/loongarch_extioi.c | 49 +++--
hw/intc/loongarch_extioi_kvm.c | 140
hw/intc/loongarch_ipi.c | 29
From: Bibo Mao
If kvm_irqchip_in_kernel() return true, interrupt controller
ExtIOI, IPI, PCH_PCI and PCH_MSI should be emlated in kernel. And
it is not necessary to create memory region for these devices in
user space.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID
From: Bibo Mao
Add save and store funtction if kvm_irqchip_in_kernel() return true,
it is to get and set ExtIOI irqchip state from KVM kernel.
Reviewed-by: Song Gao
Signed-off-by: Bibo Mao
Message-ID: <20250606063033.2557365-3-maob...@loongson.cn>
Signed-off-by: Song Gao
---
h
when loongarch cpu set irq is INT_AVEC, we need set CSR_ECFG MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 5 +++--
target/loongarch/cpu.c | 1 +
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
-off-by: Song Gao
---
hw/loongarch/virt.c | 43 +
include/hw/loongarch/virt.h | 15 +
2 files changed, 54 insertions(+), 4 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 90d4643721..3ad165af36 100644
--- a/hw
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 1 +
target/loongarch/cpu.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 21 +
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3 files changed, 32 insertions(+), 3 deletions
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 7 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 5 +
3 files changed, 22 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
]:https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loongarch-avec.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 4
include/hw/loongarch/virt.h | 20
target/loongarch/cpu.h | 21 -
3 files changed, 24 insertions
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 25
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1
Implement avec set irq and update CSR_MSIS and CSR_MSGIR.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index 7dd8bac696..bbd1b48c7d
n avec is enabled and drop patch 7;
4: Add misc_feature and misc_status for misc features an misc
fetures status
5: Define CSR_ESTAT and CSR_ECFG bit15 for msg interupt. clean patch9.
6: Fix test demsg error.
Thanks.
Song Gao
Song Gao (9):
hw/loongarch: move some machine define
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1
From: Qiang Ma
Commit bab27ea2e3 ("hw/arm/virt: smbios:
inform guest of kvm") fixes the same issue
on arm.
without this patch:
[root@localhost ~]# virt-what
qemu
with this patch:
[root@localhost ~]# virt-what
kvm
Signed-off-by: Qiang Ma
Reviewed-by: Bibo Mao
Reviewed-by: Song Ga
garch/virt: Remove global variables about initrd
hw/loongarch/virt: Remove global variables about memmap tables
Qiang Ma (1):
hw/loongarch/virt: inform guest of kvm
Song Gao (1):
target/loongarch: add check for fcond
hw/intc/loongarch_pch_pic.c | 2 +-
hw
Reviewed-by: Song Gao
Message-Id: <20250605092848.1550985-1-maob...@loongson.cn>
Signed-off-by: Song Gao
---
include/hw/intc/loongarch_extioi_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/intc/loongarch_extioi_common.h
b/include/h
g endian host
machine with TCG method.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250604065502.1114098-3-maob...@loongson.cn>
Signed-off-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/loongarch_
fcond only has 22 types, add a check for fcond.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2972
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id: <20250603024810.350510-1-gaos...@loongson.cn>
---
.../loongarch/tcg/insn_trans/trans_fcmp.c.in
big endian host
machine S390.
Fixes: 735143f10d3e ("hw/loongarch: Add acpi ged support")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250604065502.1114098-2-maob...@loongson.cn>
Signed-off-by: Song Gao
---
hw/loongarch/virt-acpi-build.c
From: Bibo Mao
Global variables memmap_table and memmap_entries stores UEFI memory
map table informations. It can be moved into structure
LoongArchVirtMachineState.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250430094738.1556670-3-maob...@loongson.cn>
Signed-off-by: So
From: Bibo Mao
Global variables initrd_offset and initrd_size records loading information
about initrd, it can be moved to structure loongarch_boot_info.
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20250430094738.1556670-2-maob...@loongson.cn>
Signed-off-by
we use CSR_ESTAT and CSR_ECFG bit 15 for msg interrupt.
and loongarch_cpu_do_interrupt support msg interrupts.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 ++-
target/loongarch/cpu.c | 35 ++-
2 files changed, 32 insertions(+), 6 deletions
-loongarch-avec.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 4
target/loongarch/cpu.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 1b504047db..90d4643721 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -548,6 +548,8
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 7 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 5 +
3 files changed, 22 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
the AVEC controller use 2ff0-2fff Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 25
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1 +
4
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 718b5b4f92..6b670e7936 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -503,11 +503,19 @@ static
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 1 +
target/loongarch/cpu.c | 17 +
2 files changed, 18 insertions(+)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 0834e91f30..83f6cb081a 100644
--- a/target/loongarch/cpu-csr.h
+++ b
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1
the AVEC controller supports 256*256 irqs, all the irqs connect CPU INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 28
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3 files changed, 39 insertions(+), 3 deletions
h
Feel free to point out any flaws!
thanks.
Song Gao
Song Gao (10):
hw/loongarch: add a new type iocsr read for Avdance interrupt
controller
loongarch: add virt feature avecintc support
loongarch: add a advance interrupt controller device
target/loongarch: add msg interrupt CSR reg
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 37 ++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index c692fef43c..f609ed9aaa 100644
--- a/hw/intc/loongarch_avec.c
+++ b/hw/intc
LoongArchVirtMachinState add avecintc features, and
it use to check whether virt machine support advance interrupt controller
and default is on.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 31 +++
include/hw/loongarch/virt.h | 9 +
2 files
/3A5000 we got a "Illegal instruction" error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2971
Fixes: 29bb5d727ff ("target/loongarch: Implement vldi")
Cc: qemu-sta...@nongnu.org
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/tcg/insn_t
/3A5000 we got a "Illegal instruction" error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2971
Fixes: 29bb5d727ff ("target/loongarch: Implement vldi")
Signed-off-by: Song Gao
---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 12 ++--
1 file changed,
we got a "Illegal instruction" error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2971
Signed-off-by: Song Gao
---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/tcg/
we got a "Illegal instruction" error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2971
Signed-off-by: Song Gao
---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/target/loongarch/tcg/
fcond only has 22 types, add a check for fcond.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2972
Signed-off-by: Song Gao
---
.../loongarch/tcg/insn_trans/trans_fcmp.c.inc | 25 +--
.../loongarch/tcg/insn_trans/trans_vec.c.inc | 16 +---
2 files changed, 30
we got a "Illegal instruction" error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2971
Signed-off-by: Song Gao
---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/loongarch/tcg/
fcond only has 22 types, add a check for fcond.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2972
Signed-off-by: Song Gao
---
target/loongarch/tcg/insn_trans/trans_fcmp.c.inc | 11 ---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 4 ++--
2 files changed, 10 insertions
we got a "Illegal instruction" error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2971
Signed-off-by: Song Gao
---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/loongarch/tcg/insn_trans/trans_ve
From: Bibo Mao
Add iomem32_high region register write operation emulation in generic
write function loongarch_pch_pic_write(), and use this function for
iomem32_high region.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250507023148.1877287-12-maob...@loongson.cn>
Signed-
.cn>
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 52 +
1 file changed, 43 insertions(+), 9 deletions(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 0324d6adcb..9b6292eaa1 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/
From: Bibo Mao
Since memory region iomem supports memory access size with 1/2/4/8,
it can be used for memory region iomem8 and iomem32_high. Now remove
memory region iomem8 and iomem32_high, merge them into iomem together.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id
From: Bibo Mao
The original iomem region only supports 4 bytes access size, set it ok
with 1/2/4/8 bytes. Also unaligned memory access is not supported.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250507023754.1877445-4-maob...@loongson.cn>
Signed-off-by: Song Gao
-
Mao
Reviewed-by: Clement Mathieu--Drif
Reviewed-by: Song Gao
Message-Id: <20250507023148.1877287-2-maob...@loongson.cn>
Signed-off-by: Song Gao
---
hw/intc/loongarch_pch_pic.c| 50 +-
hw/loongarch/virt.c| 2 +-
include/h
The following changes since commit 69ee0189d7977cfbb1b2c7a27393d8b9fb661b20:
Merge tag 'qtest-20250509-pull-request' of https://gitlab.com/farosas/qemu
into staging (2025-05-12 11:11:37 -0400)
are available in the Git repository at:
https://github.com/gaosong715/qemu.git tags/pull-loongarch
From: Bibo Mao
Register PCH_PIC_INT_ID constains version and supported irq number
information, and it is read only register. The detailed value can
be set at initial stage, rather than read callback.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250507023148.1877287-5-m
From: Bibo Mao
Add iomem8 region register read operation emulation in generic read
function loongarch_pch_pic_read(), and use this function for iomem8
region.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250507023148.1877287-10-maob...@loongson.cn>
Signed-off-by: So
From: Bibo Mao
Parameter address for read and write callback in MemoryRegionOps is
relative offset with base address of this MemoryRegionOps. It can
be directly used as offset and offset calculation can be removed.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id
From: Bibo Mao
Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_ENTRY_OFFSET is renamed
as PCH_PIC_HTMSI_VEC and PCH_PIC_ROUTE_ENTRY separately, it is easier to
understand.
Signed-off-by: Bibo Mao
Reviewed-by: Clement Mathieu--Drif
Reviewed-by: Song Gao
Message-Id: <20250507023148.187728
ed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250507023754.1877445-3-maob...@loongson.cn>
Signed-off-by: Song Gao
---
hw/intc/loongarch_pch_pic.c| 26 +++---
include/hw/intc/loongarch_pic_common.h | 2 +-
2 files changed, 8 insertions(+), 20 del
From: Bibo Mao
Add iomem8 region register write operation emulation in generic write
function loongarch_pch_pic_write(), and use this function for iomem8
region.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250507023754.1877445-1-maob...@loongson.cn>
Signed-off-by: So
From: Bibo Mao
Add register read operation emulation in generic read function
loongarch_pch_pic_read(), and use this function for iomem32_high region.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250507023148.1877287-9-maob...@loongson.cn>
Signed-off-by: Song Gao
---
h
From: Bibo Mao
The meaning of macro definition STATUS_LO_START is simliar with
PCH_PIC_INT_STATUS, only that offset is different, the same for
macro POL_LO_START. Now remove these duplicated macro definitions.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-Id: <20250507023148.187728
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