[PATCH] Fix incorrect disassembly format for certain RISC-V instructions

on the following assembly reference: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md Signed-off-by: Simeon Krastnikov --- disas/riscv.c | 144 ++ disas/riscv.h | 10 ++-- 2 files changed, 79 insertions(+), 75 deletions(-) d

[PATCH] Fix incorrect disassembly format for certain RISC-V instructions

e following assembly reference: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md Signed-off-by: Simeon Krastnikov --- disas/riscv.c | 144 ++ disas/riscv.h | 10 ++-- 2 files changed, 79 insertions(+), 75 deletions(-) d