Hi Alex,
Thanks and Sorry about the delay in responding. I had to figure out
many nuances for answering your questions.
Replies inline..
On 2/1/25 3:32 AM, Alex Williamson wrote:
On Fri, 31 Jan 2025 17:15:01 +
Shivaprasad G Bhat wrote:
Currently, the PCI_INTERRUPT_PIN alone is checked
G Bhat
---
Changelog:
v1:
https://lore.kernel.org/qemu-devel/173834353589.1880.3587671276264097972.st...@linux.ibm.com/
- Split the fix into two parts as suggested. Kernel part posted here [1]
- Changed to use the irq_info for checking the intx availability.
[1]:
https://lore.kernel.org/all
to ensure any bug there is
caught.
Resolves: Coverity CID 1593722
Fixes: 5f361ea187ba ("ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine")
Cc: Shivaprasad G Bhat
Cc: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 1 +
1 file changed, 1 insertion(+)
diff
lines are not connected on all devices under a
PCIe switch. In this configuration where the PIN is non-zero
but the LINE was 0xff, the VFIO_DEVICE_SET_IRQS was failing as
it was trying to map the irqfd for the LSI of the device.
Signed-off-by: Shivaprasad G Bhat
---
hw/vfio/pci.c |4 ++--
1
Hi David, Nick,
Sorry about not getting back on this for long!
On 2/28/24 2:22 AM, David Gibson wrote:
On Tue, Feb 27, 2024 at 10:21:23PM +1000, Nicholas Piggin wrote:
On Fri Feb 2, 2024 at 12:46 AM AEST, Shivaprasad G Bhat wrote:
As per the PAPR, bit 0 of byte 64 in pa-features property
it.
- Split the header file changes into separate patch. (Sync
headers from v5.12-rc3)
Shivaprasad G Bhat (2):
ppc: Enable 2nd DAWR support on Power10 PowerNV machine
ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine
hw/ppc/spapr.c | 7 -
hw/ppc/spapr_caps
ature bit in guest DT using cap-dawr1 machine capability.
Reviewed-by: Nicholas Piggin
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Ravi Bangoria
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr.c |7 ++-
hw/ppc/spapr_caps.c| 43 ++
Extend the existing watchpoint facility from TCG DAWR0 emulation
to DAWR1 on POWER10.
Reviewed-by: Nicholas Piggin
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Shivaprasad G Bhat
---
---
target/ppc/cpu.c | 45 +--
target/ppc/cpu.h |6
On 10/28/24 11:28 AM, Akihiko Odaki wrote:
On 2024/10/28 12:08, Shivaprasad G Bhat wrote:
On 10/22/24 2:06 PM, Akihiko Odaki wrote:
Disabled means it is a disabled SR-IOV VF and hidden from the guest.
Do not create DT when starting the system and also keep the disabled
PCI
device not
On 10/22/24 2:06 PM, Akihiko Odaki wrote:
Disabled means it is a disabled SR-IOV VF and hidden from the guest.
Do not create DT when starting the system and also keep the disabled PCI
device not linked to DRC, which generates DT in case of hotplug.
Signed-off-by: Akihiko Odaki
---
hw/ppc/sp
On 10/11/24 10:52 PM, Shivaprasad G Bhat wrote:
On 9/18/24 7:57 PM, Cédric Le Goater wrote:
Hello,
Adding :
Harsh for QEMU/PPC pseries machine,
Shivaprasad for KVM/PPC VFIO and IOMMU support.
Could you please give us your feedback on these changes ?
Thanks,
C.
On 9/13/24 05:44
On 10/12/24 5:40 PM, Akihiko Odaki wrote:
On 2024/10/12 2:22, Shivaprasad G Bhat wrote:
On 9/18/24 7:57 PM, Cédric Le Goater wrote:
Adding :
Harsh for QEMU/PPC pseries machine,
Shivaprasad for KVM/PPC VFIO and IOMMU support.
Thanks,
C.
On 9/13/24 05:44, Akihiko Odaki wrote:
A PF
disabled SR-IOV VF or it is powered off, and
hidden from the guest.
I see you are taking care of not powering on VFs in the following 8th
patch in
the series. Without it, this patch doesn't hold. Hope this patch and the
8th patch
go together.
Reviewed-by: Shivaprasad G Bhat
T
On 9/18/24 7:57 PM, Cédric Le Goater wrote:
Adding :
Harsh for QEMU/PPC pseries machine,
Shivaprasad for KVM/PPC VFIO and IOMMU support.
Thanks,
C.
On 9/13/24 05:44, Akihiko Odaki wrote:
A PF may automatically create VFs and the PF may be function 0.
Signed-off-by: Akihiko Odaki
---
On 6/28/24 4:07 PM, Cédric Le Goater wrote:
...
Could you clarify which tree you are referring to ? I see his tree
https://github.com/awilliam/tests is bit old and updated recently,
however
I have been using those tests for my unit testing.
Yes, this tree.
Thanks!
...
This went throug
On 6/21/24 8:40 PM, Cédric Le Goater wrote:
On 6/21/24 4:47 PM, Shivaprasad G Bhat wrote:
On 6/21/24 2:19 PM, Cédric Le Goater wrote:
Could you please describe the host/guest OS, hypervisor, processor
and adapter ?
Here is the environment info,
pSeries:
Host : Power10 PowerVM Lpar
On 6/21/24 2:19 PM, Cédric Le Goater wrote:
Could you please describe the host/guest OS, hypervisor, processor
and adapter ?
Here is the environment info,
pSeries:
Host : Power10 PowerVM Lpar
Kernel: Upstream 6.10.0-rc4 + VFIO fixes posted at
171810893836.1721.2640631616827396553.st...
Hi Cédric,
On 6/20/24 6:37 PM, Cédric Le Goater wrote:
Shivaprasad,
On 5/9/24 9:14 PM, Shivaprasad G Bhat wrote:
The commit 6ad359ec29 "(vfio/spapr: Move prereg_listener into
spapr container)" began to use the newly introduced VFIOSpaprContainer
structure.
After several refactors,
The patch enables HASHPKEYR migration by hooking with the
"KVM one reg" ID KVM_REG_PPC_HASHPKEYR.
Signed-off-by: Shivaprasad G Bhat
---
target/ppc/cpu_init.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index
The patch enables DEXCR migration by hooking with the
"KVM one reg" ID KVM_REG_PPC_DEXCR.
Signed-off-by: Shivaprasad G Bhat
---
target/ppc/cpu_init.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index
The patch enables HASHKEYR migration by hooking with the
"KVM one reg" ID KVM_REG_PPC_HASHKEYR.
Signed-off-by: Shivaprasad G Bhat
---
target/ppc/cpu_init.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index
This is a placeholder change for these SPRs until the full linux
header update.
Signed-off-by: Shivaprasad G Bhat
---
linux-headers/asm-powerpc/kvm.h |3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index 1691297a76
SHPKEYR as suggested
Shivaprasad G Bhat (4):
linux-header: PPC: KVM: Update one-reg ids for DEXCR, HASHKEYR and
HASHPKEYR
target/ppc/cpu_init: Synchronize DEXCR with KVM for migration
target/ppc/cpu_init: Synchronize HASHKEYR with KVM for migration
target/ppc/cpu_init: S
take care of this. Also, the PPC
kvm header changes are selectively picked for the required
definitions posted here at [2].
References:
[1]: https://github.com/kvm-unit-tests/kvm-unit-tests
[2]:
https://lore.kernel.org/kvm/171741323521.6631.11242552089199677395.st...@linux.ibm.com
---
Shivaprasad
The patch enables DEXCR migration by hooking with the
"KVM one reg" ID KVM_REG_PPC_DEXCR.
Signed-off-by: Shivaprasad G Bhat
---
linux-headers/asm-powerpc/kvm.h |1 +
target/ppc/cpu_init.c |4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/linux-h
The patch enables HASHKEYR migration by hooking with the
"KVM one reg" ID KVM_REG_PPC_HASHKEYR.
Signed-off-by: Shivaprasad G Bhat
---
linux-headers/asm-powerpc/kvm.h |1 +
target/ppc/cpu_init.c |4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --g
On 5/13/24 17:53, Cédric Le Goater wrote:
Hello Shivaprasad,
On 5/9/24 21:14, Shivaprasad G Bhat wrote:
The commit 6ad359ec29 "(vfio/spapr: Move prereg_listener into
spapr container)" began to use the newly introduced VFIOSpaprContainer
structure.
After several refactors,
ener into spapr container)"
Signed-off-by: Shivaprasad G Bhat
---
hw/vfio/container.c |6 --
hw/vfio/spapr.c |6 --
include/hw/vfio/vfio-common.h |6 ++
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/vfio/container.c b/hw/vf
Thanks for the review Nick!
On 1/23/24 17:36, Nicholas Piggin wrote:
On Wed Nov 22, 2023 at 5:32 PM AEST, Shivaprasad G Bhat wrote:
Extend the existing watchpoint facility from TCG DAWR0 emulation
to DAWR1 on POWER10.
As per the PAPR, bit 0 of byte 64 in pa-features property
indicates
Extend the existing watchpoint facility from TCG DAWR0 emulation
to DAWR1 on POWER10.
Signed-off-by: Shivaprasad G Bhat
---
target/ppc/cpu.c | 45 --
target/ppc/cpu.h |8 +-
target/ppc/cpu_init.c| 15 +++
target/ppc
ature bit in guest DT using cap-dawr1 machine capability.
Signed-off-by: Ravi Bangoria
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr.c |7 ++-
hw/ppc/spapr_caps.c| 36
hw/ppc/spapr_hcall.c | 25 -
include/h
roduce machine capability cap-dawr1 to enable/disable
the feature. By default, 2nd DAWR is OFF for guests even
when host kvm supports it. User has to manually enable it
with -machine cap-dawr1=on if he wishes to use it.
- Split the header file changes into separate patch. (Sync
heade
whether kvm supports 2nd DAWR or not. If it's supported, allow user to set
the pa-feature bit in guest DT using cap-dawr1 machine capability.
Signed-off-by: Ravi Bangoria
Signed-off-by: Shivaprasad G Bhat
---
Changelog:
v6:
https://lore.kernel.org/qemu-devel/168871963321.58984.156283826146212
On 7/7/23 19:54, Cédric Le Goater wrote:
On 7/7/23 13:59, Greg Kurz wrote:
Hi Daniel and Shiva !
On Fri, 7 Jul 2023 08:09:47 -0300
Daniel Henrique Barboza wrote:
This one was a buzzer shot.
Indeed ! :-) I would have appreciated some more time to re-assess
my R-b tag on this 2 year old b
s patch got lucky then. If you/Cedric remove your acks I would
simply drop the
patch and re-send the PR with the greatest of ease, no remorse
whatsoever.
Thanks,
Daniel
Cheers,
--
Greg
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/7/23 05:47, Shivaprasad G Bh
er to set
the pa-feature bit in guest DT using cap-dawr1 machine capability. Though,
watchpoint on powerpc TCG guest is not supported and thus 2nd DAWR is not
enabled for TCG mode.
Signed-off-by: Ravi Bangoria
Reviewed-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Signed-off-by: Shivaprasad G
Hi David, All,
I am revisiting/reviving this patch.
On 5/5/21 11:20, David Gibson wrote:
On Wed, Apr 21, 2021 at 11:50:40AM +0530, Ravi Bangoria wrote:
Hi David,
On 4/19/21 10:23 AM, David Gibson wrote:
On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
Since we have released
-by: Shivaprasad G Bhat
Reviewed-by: Lucas Mateus Castro
---
tests/tcg/ppc64/Makefile.target |5 +++-
tests/tcg/ppc64/vector.c| 51 +++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/ppc64/vector.c
diff --git a/tests
1ULL instead of signed int 1 like its
used everywhere else.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1536
Signed-off-by: Shivaprasad G Bhat
Reviewed-by: Alex Bennée
Reviewed-by: Lucas Mateus Castro
Reviewed-by: Richard Henderson
---
target/ppc/translate/vmx-impl.c.inc |2 +-
1
BIG_ENDIAN from compiler.h
Shivaprasad G Bhat (2):
tcg: ppc64: Fix mask generation for vextractdm
tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions
target/ppc/translate/vmx-impl.c.inc | 2 +-
tests/tcg/ppc64/Makefile.target | 6 +++-
tests/tcg/ppc6
Hi Richard,
On 5/3/23 01:11, Richard Henderson wrote:
On 5/2/23 16:25, Shivaprasad G Bhat wrote:
The float32_exp2() is computing wrong exponent of 2.
For example, with the following set of values {0.1, 2.0, 2.0, -1.0},
the expected output would be {1.071773, 4.00, 4.00, 0.50
On 5/2/23 12:35, Cédric Le Goater wrote:
On 4/13/23 21:01, Shivaprasad G Bhat wrote:
Add test for vextractbm, vextractwm, vextractdm and vextractqm
instructions. Test works for both qemu-ppc64 and qemu-ppc64le.
Based on the test case written by John Platts posted at [1]
References:
[1]: https
ttps://gitlab.com/lu-zero)
Signed-off-by: Shivaprasad G Bhat
Signed-off-by: Vaibhav Jain
---
fpu/softfloat.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index c7454c3eb1a..108f9cb224a 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@
: Shivaprasad G Bhat
---
tests/tcg/ppc64/Makefile.target |6 -
tests/tcg/ppc64/vector.c| 50 +++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/ppc64/vector.c
diff --git a/tests/tcg/ppc64/Makefile.target b/tests
1ULL instead of signed int 1 like its
used everywhere else.
Signed-off-by: Shivaprasad G Bhat
---
target/ppc/translate/vmx-impl.c.inc |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 112233b541..c
sed in multiarch/sha1.c also this being arch specific
test, I think it is appropriate to use it here. Let me
know if otherwise.
References:
[1] : https://gitlab.com/qemu-project/qemu/-/issues/1536
---
Shivaprasad G Bhat (2):
tcg: ppc64: Fix mask generation for vextractdm
tests: tcg: ppc6
es with failures.
Signed-off-by: Shivaprasad G Bhat
Reviewed-by: Daniel Henrique Barboza
---
hw/ppc/spapr_nvdimm.c | 132 +
1 file changed, 132 insertions(+)
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
index ac44e00153..c4c97
be introduced in the
following patch.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr.c|2
hw/ppc/spapr_nvdimm.c | 260 +
include/hw/ppc/spapr.h|4 -
include/hw/ppc/spapr_nvdimm.h |1
4 files changed,
A new subclass inheriting NVDIMMDevice is going to be introduced in
subsequent patches. The new subclass uses the realize and unrealize
callbacks. Add them on NVDIMMClass to appropriately call them as part
of plug-unplug.
Signed-off-by: Shivaprasad G Bhat
Acked-by: Daniel Henrique Barboza
anges from v1
- Fixed a missed-out unlock
- using QLIST_FOREACH instead of QLIST_FOREACH_SAFE while generating token
Shivaprasad G Bhat (3):
nvdimm: Add realize, unrealize callbacks to NVDIMMDevice class
spapr: nvdimm: Implement H_SCM_FLUSH hcall
spapr: nvdimm: Introduce spap
es with failures.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c | 131 +
1 file changed, 131 insertions(+)
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
index ed6fda2c23..8aa6214d6b 100644
--- a/hw/ppc/spapr_nvdimm.c
++
A new subclass inheriting NVDIMMDevice is going to be introduced in
subsequent patches. The new subclass uses the realize and unrealize
callbacks. Add them on NVDIMMClass to appropriately call them as part
of plug-unplug.
Signed-off-by: Shivaprasad G Bhat
---
hw/mem/nvdimm.c | 16
- Fixed a missed-out unlock
- using QLIST_FOREACH instead of QLIST_FOREACH_SAFE while generating token
Shivaprasad G Bhat (3):
nvdimm: Add realize, unrealize callbacks to NVDIMMDevice class
spapr: nvdimm: Implement H_SCM_FLUSH hcall
spapr: nvdimm: Introduce spapr-nvdim
On 9/21/21 12:02, David Gibson wrote:
On Wed, Jul 07, 2021 at 09:57:31PM -0500, Shivaprasad G Bhat wrote:
If the device backend is not persistent memory for the nvdimm, there is
need for explicit IO flushes on the backend to ensure persistence.
On SPAPR, the issue is addressed by adding a
Hi David,
Thanks for comments. Sorry about the delay. Replies inline.
On 9/21/21 11:53, David Gibson wrote:
On Wed, Jul 07, 2021 at 09:57:21PM -0500, Shivaprasad G Bhat wrote:
The patch adds support for the SCM flush hcall for the nvdimm devices.
To be available for exploitation by guest
be introduced in the
following patch.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr.c|2
hw/ppc/spapr_nvdimm.c | 263 +
include/hw/ppc/spapr.h|4 -
include/hw/ppc/spapr_nvdimm.h |1
4 files changed,
backend doesn't have
pmem="yes", the device tree property "ibm,hcall-flush-required" is set,
and the guest makes hcall H_SCM_FLUSH requesting for an explicit flush.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c | 46
on in post_load. The necessary nvdimm flush specific
vmstate structures are added to the spapr machine vmstate.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr.c|6 +
hw/ppc/spapr_nvdimm.c | 240 +
include/hw/ppc/spapr.h| 1
- Miscellanious minor fixes.
v1 - https://lists.gnu.org/archive/html/qemu-devel/2020-11/msg06330.html
Changes from v1
- Fixed a missed-out unlock
- using QLIST_FOREACH instead of QLIST_FOREACH_SAFE while generating token
Shivaprasad G Bhat (2):
spapr: nvdimm: Implement H_
ld fail, so fix that.
Reported-by: Aneesh Kumar K.V
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
index 252204e25f..d7a4a0a051 100644
--- a/hw/ppc/spapr_n
on in post_load. The necessary nvdimm flush specific
vmstate structures are added to the spapr machine vmstate.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr.c|6 +
hw/ppc/spapr_nvdimm.c | 240 +
include/hw/ppc/spapr.h| 1
The subsequent patches add definitions which tend to get
the compilation to cyclic dependency. So, prepare with
forward declarations, move the definitions and clean up.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c | 12
include/hw/ppc/spapr_nvdimm.h | 14
- Added hw_compat magic for sync-dax 'on' on previous machines.
- Miscellanious minor fixes.
v1 - https://lists.gnu.org/archive/html/qemu-devel/2020-11/msg06330.html
Changes from v1
- Fixed a missed-out unlock
- using QLIST_FOREACH instead of QLIST_FOREACH_SAFE
backend doesn't have
pmem="yes", the device tree property "ibm,hcall-flush-required" is set,
and the guest makes hcall H_SCM_FLUSH requesting for an explicit flush.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c | 46
On 5/1/21 12:44 AM, Dan Williams wrote:
Some corrections to terminology confusion below...
On Wed, Apr 28, 2021 at 8:49 PM Shivaprasad G Bhat wrote:
The nvdimm devices are expected to ensure write persistence during power
failure kind of scenarios.
No, QEMU is not expected to make that
e guest to issue H_SCM_FLUSH hcalls to request for flushes
explicitly. This would be the default behaviour without sync-dax
property set for the nvdimm device. For old pSeries machine, the
default is 'unsafe'.
For non-PPC platforms, the mode is set to 'unsafe' as the default.
The necessary
nvdimm flush specific vmstate structures are added to the spapr
machine vmstate.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr.c|6 +
hw/ppc/spapr_nvdimm.c | 234 +
include/hw/ppc/spapr.h| 1
The subsequent patches add definitions which tend to
get the compilation to cyclic dependency. So, prepare
with forward declarations, move the defitions and clean up.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c | 12
include/hw/ppc/spapr_nvdimm.h | 14
minor fixes.
v1 - https://lists.gnu.org/archive/html/qemu-devel/2020-11/msg06330.html
Changes from v1
- Fixed a missed-out unlock
- using QLIST_FOREACH instead of QLIST_FOREACH_SAFE while generating token
Shivaprasad G Bhat (3):
spapr: nvdimm: Forward declare and move the definitio
Hi Vaibhav,
Some comments inline..
On 3/29/21 9:52 PM, Vaibhav Jain wrote:
Add support for H_SCM_HEALTH hcall described at [1] for spapr
nvdimms. This enables guest to detect the 'unarmed' status of a
specific spapr nvdimm identified by its DRC and if its unarmed, mark
the region backed by the
On 3/24/21 8:37 AM, David Gibson wrote:
On Tue, Mar 23, 2021 at 09:47:38AM -0400, Shivaprasad G Bhat wrote:
machine vmstate.
Signed-off-by: Shivaprasad G Bhat
An overal question: surely the same issue must arise on x86 with
file-backed NVDIMMs. How do they handle this case?
Discussed in
On 3/25/21 7:21 AM, David Gibson wrote:
On Wed, Mar 24, 2021 at 09:34:06AM +0530, Aneesh Kumar K.V wrote:
On 3/24/21 8:37 AM, David Gibson wrote:
On Tue, Mar 23, 2021 at 09:47:38AM -0400, Shivaprasad G Bhat wrote:
The patch adds support for the SCM flush hcall for the nvdimm devices
eted' list. The necessary
nvdimm flush specific vmstate structures are added to the spapr
machine vmstate.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr.c|6 +
hw/ppc/spapr_nvdimm.c | 240 +
include/hw/ppc/spapr.h
the default behaviour without sync-dax property set
for the nvdimm device.
The sync-dax="on" would mean the guest need not make flush requests
to the qemu. On previous machine versions the sync-dax is set to be
"on" by default using the hw_compat magic.
Signed-off-by: Shivaprasad
The subsequent patches add definitions which tend to
get the compilation to cyclic dependency. So, prepare
with forward declarations, move the defitions and clean up.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c | 12
include/hw/ppc/spapr_nvdimm.h | 21
all ongoning flushes.
- Added hw_compat magic for sync-dax 'on' on previous machines.
- Miscellanious minor fixes.
v1 - https://lists.gnu.org/archive/html/qemu-devel/2020-11/msg06330.html
Changes from v1
- Fixed a missed-out unlock
- using QLIST_FOREACH instead of
Hi David,
Sorry about the delay.
On 2/8/21 11:51 AM, David Gibson wrote:
On Tue, Jan 19, 2021 at 12:40:31PM +0530, Shivaprasad G Bhat wrote:
Thanks for the comments!
On 12/28/20 2:08 PM, David Gibson wrote:
On Mon, Dec 21, 2020 at 01:08:53PM +0100, Greg Kurz wrote:
...
The overall idea
Thanks for the comments!
On 12/28/20 2:08 PM, David Gibson wrote:
On Mon, Dec 21, 2020 at 01:08:53PM +0100, Greg Kurz wrote:
...
The overall idea looks good but I think you should consider using
a thread pool to implement it. See below.
I am not convinced, however. Specifically, attaching
enables explicit asynchronous
flush requests from guest. It can be disabled by setting syn-dax=on.
Signed-off-by: Shivaprasad G Bhat
---
hw/mem/nvdimm.c |1 +
hw/ppc/spapr_nvdimm.c | 79 +++
include/hw/mem/nvdimm.h | 10 ++
include/hw
The patch adds support for async hcalls at the DRC level for the
spapr devices. To be used by spapr-scm devices in the patch/es to follow.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_drc.c | 149
include/hw/ppc/spapr_drc.h | 25
30.html
Changes from v1
- Fixed a missed-out unlock
- using QLIST_FOREACH instead of QLIST_FOREACH_SAFE while generating token
Shivaprasad G Bhat (2):
spapr: drc: Add support for async hcalls at the drc level
spapr: nvdimm: Implement async flush hcalls
hw/mem/nvdimm.c
enables explicit asynchronous
flush requests from guest. It can be disabled by setting syn-dax=on.
Signed-off-by: Shivaprasad G Bhat
---
hw/mem/nvdimm.c |1 +
hw/ppc/spapr_nvdimm.c | 79 +++
include/hw/mem/nvdimm.h | 10 ++
include/hw
The patch adds support for async hcalls at the DRC level for the
spapr devices. To be used by spapr-scm devices in the patch/es to follow.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_drc.c | 146
include/hw/ppc/spapr_drc.h | 25
s,inode64,logbufs=8,logbsize=32k,noquota)
[root@atest-guest ~]# ./mapsync /mnt1/newfile> When sync-dax=off
[root@atest-guest ~]# ./mapsync /mnt2/newfile> when sync-dax=on
Failed to mmap with Operation not supported
---
Shivaprasad G Bhat (2):
spapr: drc: Add support for
On 05/05/2020 03:48 PM, Markus Armbruster wrote:
nvdimm_set_uuid() leaks memory on qemu_uuid_parse() failure. Fix
that.
Fixes: 6c5627bb24dcd68c997857a8b671617333b1289f
Cc: Xiao Guangrong
Cc: Shivaprasad G Bhat
Signed-off-by: Markus Armbruster
Thanks for finding and fixing this Markus
On 02/27/2020 05:58 PM, Greg Kurz wrote:
On Wed, 26 Feb 2020 13:49:27 +0100
Greg Kurz wrote:
-qemu_uuid_parse(uuidstr, &uuid);
... cause a segv in there because uuidstr will be dereferenced at
some point without checking if it's NULL.
AFAICT there are two scenarios that can cause object_
tion again.
As this a false positive in this case, assert if not valid to be safe.
Also, error_abort if QOM accessor encounters error while fetching the uuid
property.
Reported-by: Coverity (CID 1419883)
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c |7 +--
1 file changed, 5
On 02/25/2020 03:30 PM, Peter Maydell wrote:
On Fri, 21 Feb 2020 at 03:37, David Gibson wrote:
From: Shivaprasad G Bhat
Add support for NVDIMM devices for sPAPR. Piggyback on existing nvdimm
device interface in QEMU to support virtual NVDIMM devices for Power.
+}
+
+uuidstr
tion again.
As this a false positive in this case, assert if not valid to be safe.
Reported-by: Coverity (CID 1419883)
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdi
safe to
do bind/unbind everything during the device_add/del.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/spapr_nvdimm.c | 298
include/hw/ppc/spapr.h |8 +
2 files changed, 305 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_nvdim
For ppc64, PAPR requires the nvdimm device to have UUID property
set in the device tree. Add an option to get it from the user.
Signed-off-by: Shivaprasad G Bhat
Reviewed-by: David Gibson
Reviewed-by: Igor Mammedov
---
hw/mem/nvdimm.c | 40
-backend-file,id=memnvdimm0,prealloc=yes,mem-path=/tmp/nvdimm0,share=yes,size=1073872896
device_add
nvdimm,label-size=128k,uuid=75a3cdd7-6a2f-4791-8d15-fe0a920e8e9e,memdev=memnvdimm0,id=nvdimm0,slot=0
Signed-off-by: Shivaprasad G Bhat
Signed-off-by: Bharata B Rao
[Early
nvdimm_device_list is required for parsing the list for devices
in subsequent patches. Move it to common utility area.
Signed-off-by: Shivaprasad G Bhat
Reviewed-by: Igor Mammedov
Reviewed-by: David Gibson
---
hw/acpi/nvdimm.c| 28 +---
include/qemu
different kinds of checks and return
different values.
- Addressed comments for v1
---
Shivaprasad G Bhat (4):
mem: move nvdimm_device_list to utilities
nvdimm: add uuid property to nvdimm
spapr: Add NVDIMM device support
spapr: Add Hcalls to support PAPR NVDIMM device
On 02/04/2020 09:29 AM, David Gibson wrote:
On Thu, Jan 30, 2020 at 05:48:15AM -0600, Shivaprasad G Bhat wrote:
Add support for NVDIMM devices for sPAPR. Piggyback on existing nvdimm
device interface in QEMU to support virtual NVDIMM devices for Power.
Create the required DT entries for the
safe to
do bind/unbind everything during the device_add/del.
Signed-off-by: Shivaprasad G Bhat
---
hw/ppc/Makefile.objs |2
hw/ppc/spapr_nvdimm.c | 327
include/hw/ppc/spapr.h |8 +
3 files changed, 335 insertions(+), 2 dele
-backend-file,id=memnvdimm0,prealloc=yes,mem-path=/tmp/nvdimm0,share=yes,size=1073872896
device_add
nvdimm,label-size=128k,uuid=75a3cdd7-6a2f-4791-8d15-fe0a920e8e9e,memdev=memnvdimm0,id=nvdimm0,slot=0
Signed-off-by: Shivaprasad G Bhat
Signed-off-by: Bharata B Rao
[Early
On 01/03/2020 07:14 AM, David Gibson wrote:
On Tue, Dec 17, 2019 at 02:49:36AM -0600, Shivaprasad G Bhat wrote:
This patch implements few of the necessary hcalls for the nvdimm support.
Fixing all the comments.
Of course, we're not *actually* unbinding anything. But I guess the
idea
nvdimm_device_list is required for parsing the list for devices
in subsequent patches. Move it to common utility area.
Signed-off-by: Shivaprasad G Bhat
Reviewed-by: Igor Mammedov
Reviewed-by: David Gibson
---
hw/acpi/nvdimm.c| 28 +---
include/qemu
For ppc64, PAPR requires the nvdimm device to have UUID property
set in the device tree. Add an option to get it from the user.
Signed-off-by: Shivaprasad G Bhat
Reviewed-by: David Gibson
---
hw/mem/nvdimm.c | 40
include/hw/mem/nvdimm.h
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