[PATCH v2] target/riscv: set tval for triggered watchpoints

From: Sergey Matyukevich According to priviledged spec, if [sm]tval is written with a nonzero value when a breakpoint exception occurs, then [sm]tval will contain the faulting virtual address. Set tval to hit address when breakpoint exception is triggered by hardware watchpoint. Signed-off-by

Re: [PATCH] target/riscv: set tval for triggered watchpoints

is triggered by hardware watchpoint. > > > > > > Signed-off-by: Sergey Matyukevich > > > > Thanks! > > > > Applied to riscv-to-apply.next > > Oops, too quick, but I have one comment :) > > > > > Alistair > > > > > --- &g

[PATCH] target/riscv: set tval for triggered watchpoints

From: Sergey Matyukevich According to priviledged spec, if [sm]tval is written with a nonzero value when a breakpoint exception occurs, then [sm]tval will contain the faulting virtual address. Set tval to hit address when breakpoint exception is triggered by hardware watchpoint. Signed-off-by