[PATCH v3 3/6] hw/riscv: Make FDT optional for MPFS

. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 56 +++--- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index f477d2791e..844dc0545c 100644 --- a/hw/riscv/microchip_pfsoc.c

[PATCH v3 0/6] Improve Microchip Polarfire SoC customization

\ -kernel rtos.elf v2: * Add documentation update. * In patch 3, warn if no device tree is specified. * In patch 4, use riscv_find_firmware() to locate the firmware shipped with Qemu. v3: * In patch 4, add support for Qemu test runs. Sebastian Huber (6): hw/misc: Add MPFS system reset

[PATCH v3 1/6] hw/misc: Add MPFS system reset support

Signed-off-by: Sebastian Huber --- hw/misc/mchp_pfsoc_sysreg.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 7876fe0c5b..08196525aa 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -27,7

[PATCH v3 6/6] hw/riscv: microchip_pfsoc: Rework documentation

Mention that running the HSS no longer works. Document the changed boot options. Reorder documentation blocks. Update URLs. Signed-off-by: Sebastian Huber --- docs/system/riscv/microchip-icicle-kit.rst | 124 +++-- 1 file changed, 43 insertions(+), 81 deletions(-) diff --git

[PATCH v3 4/6] hw/riscv: Allow direct start of kernel for MPFS

d_firmware(). Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 59 +++--- 1 file changed, 42 insertions(+), 17 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 844dc0545c..5c9f7f643f 100644 --- a/hw/riscv/microch

[PATCH v3 2/6] hw/riscv: More flexible FDT placement for MPFS

If the kernel entry is in the high DRAM area, place the FDT into this area. Signed-off-by: Sebastian Huber Reviewed-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv

[PATCH v3 5/6] hw/riscv: Configurable MPFS CLINT timebase freq

This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=1000 Signed-off-by: Sebastian Huber Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/microchip_pfsoc.c | 49

[PATCH] hw/riscv: Fix test for microchi-icicle-kit

out! ERROR:../hw/riscv/boot.c:164:riscv_load_firmware: \ assertion failed: (firmware_filename != NULL) Use an approach similar to riscv_find_and_load_firmware(). Reported-by: Daniel Henrique Barboza Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 12 +++- 1 file

[PATCH v2 6/6] hw/riscv: microchip_pfsoc: Rework documentation

Mention that running the HSS no longer works. Document the changed boot options. Reorder documentation blocks. Update URLs. Signed-off-by: Sebastian Huber --- docs/system/riscv/microchip-icicle-kit.rst | 124 +++-- 1 file changed, 43 insertions(+), 81 deletions(-) diff --git

[PATCH v2 4/6] hw/riscv: Allow direct start of kernel for MPFS

Further customize the -bios and -kernel options behaviour for the microchip-icicle-kit machine. If "-bios none -kernel filename" is specified, then do not load a firmware and instead only load and start the kernel image. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pf

[PATCH v2 3/6] hw/riscv: Make FDT optional for MPFS

. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 56 +++--- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index f477d2791e..844dc0545c 100644 --- a/hw/riscv/microchip_pfsoc.c

[PATCH v2 2/6] hw/riscv: More flexible FDT placement for MPFS

If the kernel entry is in the high DRAM area, place the FDT into this area. Signed-off-by: Sebastian Huber Reviewed-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv

[PATCH v2 0/6] Improve Microchip Polarfire SoC customization

\ -kernel rtos.elf v2: * Add documentation update. * In patch 3, warn if no device tree is specified. * In patch 4, use riscv_find_firmware() to locate the firmware shipped with Qemu. Sebastian Huber (6): hw/misc: Add MPFS system reset support hw/riscv: More flexible FDT placement for

[PATCH v2 5/6] hw/riscv: Configurable MPFS CLINT timebase freq

This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=1000 Signed-off-by: Sebastian Huber Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/microchip_pfsoc.c | 49

[PATCH v2 1/6] hw/misc: Add MPFS system reset support

Signed-off-by: Sebastian Huber --- hw/misc/mchp_pfsoc_sysreg.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 7876fe0c5b..08196525aa 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -27,7

Re: [PATCH 3/5] hw/riscv: Make FDT optional for MPFS

- Am 24. Feb 2025 um 6:22 schrieb Alistair Francis alistai...@gmail.com: > On Fri, Feb 14, 2025 at 4:27 PM Sebastian Huber > wrote: >> >> Real-time kernels such as RTEMS or Zephyr may use a static device tree >> built into the kernel image. Do not require t

Re: [PATCH 0/5] Improve Microchip Polarfire SoC customization

- Am 20. Feb 2025 um 23:29 schrieb Philippe Mathieu-Daudé phi...@linaro.org: > Hi Conor, > > On 20/2/25 19:30, Conor Dooley wrote: >> +cc qemu-riscv, Alistar. >> >> On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: >>> Booting the microchip

[PATCH v2] hw/riscv: Allow direct start of kernel for MPFS

Further customize the -bios and -kernel options behaviour for the microchip-icicle-kit machine. If "-bios none -kernel filename" is specified, then do not load a firmware and instead only load and start the kernel image. Signed-off-by: Sebastian Huber --- v2: Use riscv_find_fir

[PATCH 2/5] hw/riscv: More flexible FDT placement for MPFS

If the kernel entry is in the high DRAM area, place the FDT into this area. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index ec7e2e4226

[PATCH 5/5] hw/riscv: Configurable MPFS CLINT timebase freq

This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=1000 Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 49 +++--- include/hw/riscv

[PATCH 0/5] Improve Microchip Polarfire SoC customization

\ -kernel rtos.elf Sebastian Huber (5): hw/misc: Add MPFS system reset support hw/riscv: More flexible FDT placement for MPFS hw/riscv: Make FDT optional for MPFS hw/riscv: Allow direct start of kernel for MPFS hw/riscv: Configurable MPFS CLINT timebase freq hw/misc

[PATCH 1/5] hw/misc: Add MPFS system reset support

Signed-off-by: Sebastian Huber --- hw/misc/mchp_pfsoc_sysreg.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 7876fe0c5b..08196525aa 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -27,7

[PATCH 4/5] hw/riscv: Allow direct start of kernel for MPFS

Further customize the -bios and -kernel options behaviour for the microchip-icicle-kit machine. If "-bios none -kernel filename" is specified, then do not load a firmware and instead only load and start the kernel image. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pf

[PATCH 3/5] hw/riscv: Make FDT optional for MPFS

Real-time kernels such as RTEMS or Zephyr may use a static device tree built into the kernel image. Do not require to use the -dtb option if -kernel is used for the microchip-icicle-kit machine. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 53

Re: [PATCH 1/2] hw/arm/boot: Use hooks if PSCI is disabled

- Am 30. Sep 2024 um 17:16 schrieb Peter Maydell peter.mayd...@linaro.org: > On Mon, 23 Sept 2024 at 04:57, Sebastian Huber > wrote: >> >> In arm_load_kernel(), use the secondary boot hooks provided by the >> platform if PSCI is disabled also while booting a no

[PATCH 1/2] hw/arm/boot: Use hooks if PSCI is disabled

resetting a non-Linux kernel. This change allows a more accurate simulation of the platform reset behaviour. Signed-off-by: Sebastian Huber --- hw/arm/boot.c | 30 +++--- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index

[PATCH 2/2] hw/arm/xilinx_zynq: Add CPU1 reset

After a system reset (SRST), the CPU1 should execute a wfe instruction and then load the start address from 0xfff0: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1 Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 25 + 1 file

[PATCH 0/2] Fix secondary CPU reset for Xilinx Zynq 7000

https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1 Sebastian Huber (2): hw/arm/boot: Use hooks if PSCI is disabled hw/arm/xilinx_zynq: Add CPU1 reset hw/arm/boot.c| 30 +++--- hw/arm/xilinx_zynq.c | 25 + 2 files change

Re: Xilinx Zynq 7000 Start of CPU1

- Am 18. Sep 2024 um 11:13 schrieb Sebastian Huber sebastian.hu...@embedded-brains.de: > Hello, > > I recently added the support for CPU1 to the xilinx-zynq-a9 machine > (hw/arm/xilinx_zynq.c). However, the reset behaviour doesn't match exactly > with > the hardwar

Xilinx Zynq 7000 Start of CPU1

0: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1 It would be great if someone has a hint for me how I can add this startup code for CPU1 at address region 0xFE00 to 0xFFF0. Kind regards, Sebastian -- embedded brains GmbH & Co. KG Herr Sebastian HUBER Dorn

Are floating-point exceptions usable on AArch64?

ouble x = 0x0; volatile double y = 0x0; x /= y; When I look with the debugger at $fpcr it still says 0x0 after the msr. Are floating-point exceptions usable on AArch64 in general? -- embedded brains GmbH & Co. KG Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebas

Re: [PATCH] hw/arm/xilinx_zynq: Enable Security Extensions

Hello Peter, - Am 29. Aug 2024 um 14:50 schrieb Peter Maydell peter.mayd...@linaro.org: > On Wed, 28 Aug 2024 at 01:51, Sebastian Huber > wrote: >> >> The system supports the Security Extensions (core and GIC). This change is >> necessary to run tests which p

[PATCH] hw/arm/xilinx_zynq: Enable Security Extensions

The system supports the Security Extensions (core and GIC). This change is necessary to run tests which pass on the real hardware. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 8 1 file changed, 8 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c

[PATCH] hw/arm/xilinx_zynq: Fix IRQ/FIQ routing

Fix the system bus interrupt line to CPU core assignment. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 7f7a3d23fb..c79661bbc1 100644 --- a/hw/arm/xilinx_zynq.c

Re: [PATCH v2 0/2] Zynq 7000 Improvements

On 30.05.24 12:30, Peter Maydell wrote: On Fri, 24 May 2024 at 13:08, Sebastian Huber wrote: v2: * Add Kconfig support * Add array of CPUs to ZynqMachineState * Add FIQ support Sebastian Huber (2): hw/arm/xilinx_zynq: Add cache controller hw/arm/xilinx_zynq: Support up to two CPU

[PATCH v2 1/2] hw/arm/xilinx_zynq: Add cache controller

The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the corresponding Qemu device to the xilinx-zynq-a9 machine. Signed-off-by: Sebastian Huber --- hw/arm/Kconfig | 1 + hw/arm/xilinx_zynq.c | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm

[PATCH v2 0/2] Zynq 7000 Improvements

v2: * Add Kconfig support * Add array of CPUs to ZynqMachineState * Add FIQ support Sebastian Huber (2): hw/arm/xilinx_zynq: Add cache controller hw/arm/xilinx_zynq: Support up to two CPU cores hw/arm/Kconfig | 1 + hw/arm/xilinx_zynq.c | 55

[PATCH v2 2/2] hw/arm/xilinx_zynq: Support up to two CPU cores

The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only one core). Add support for up to two simulated cores. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 54 +++- 1 file changed, 33 insertions(+), 21 deletions(-) diff

Re: [PATCH 2/2] hw/arm/xilinx_zynq: Support up to two CPU cores

Hello Peter, thanks for the review. On 20.05.24 15:58, Peter Maydell wrote: On Tue, 7 May 2024 at 14:04, Sebastian Huber wrote: The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only one core). Add support for up to two simulated cores. Signed-off-by: Sebastian

[PATCH v2 1/2] hw/intc/arm_gic: Fix set pending of PPIs

According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending Registers, GICD_ISPENDRn": "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected processor. This register holds the Set-pending bits for interrupts 0-31." Signed-off-by: Seba

[PATCH v2 2/2] hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn

rupt makes that interrupt pending on that CPU interface - removing a CPU interface from the target list of a pending interrupt removes the pending state of that interrupt on that CPU interface." Signed-off-by: Sebastian Huber --- hw/intc/arm_gic.c | 7 +++ 1 file changed, 7 inserti

[PATCH v2 0/2] Fix GICv2 handling of pending interrupts

v2: * Fix handling of SPIs. * Remove pending state if not in new target list. Sebastian Huber (2): hw/intc/arm_gic: Fix set pending of PPIs hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn hw/intc/arm_gic.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) -- 2.35.3

Re: [PATCH 0/2] Zynq 7000 SoC improvements

Hello, is the mailing list the right place for contributions like this? On 07.05.24 15:03, Sebastian Huber wrote: Add support for the cache controller and up to two Cortex-A9 MPCore. Sebastian Huber (2): hw/arm/xilinx_zynq: Add cache controller hw/arm/xilinx_zynq: Support up to two CPU

[PATCH 1/2] hw/arm/xilinx_zynq: Add cache controller

The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the corresponding Qemu device to the xilinx-zynq-a9 machine. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index

[PATCH 2/2] hw/arm/xilinx_zynq: Support up to two CPU cores

The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only one core). Add support for up to two simulated cores. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 42 +++--- 1 file changed, 27 insertions(+), 15 deletions(-) diff

[PATCH 0/2] Zynq 7000 SoC improvements

Add support for the cache controller and up to two Cortex-A9 MPCore. Sebastian Huber (2): hw/arm/xilinx_zynq: Add cache controller hw/arm/xilinx_zynq: Support up to two CPU cores hw/arm/xilinx_zynq.c | 43 --- 1 file changed, 28 insertions(+), 15

[PATCH 1/2] hw/intc/arm_gic: Fix set pending of PPIs

According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending Registers, GICD_ISPENDRn": "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected processor. This register holds the Set-pending bits for interrupts 0-31." Signed-off-by: Seba

[PATCH 2/2] hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn

rupt makes that interrupt pending on that CPU interface - removing a CPU interface from the target list of a pending interrupt removes the pending state of that interrupt on that CPU interface." Signed-off-by: Sebastian Huber --- hw/intc/arm_gic.c | 7 +++ 1 file changed, 7 inserti

[PATCH 1/2] hw/intc/arm_gic: Fix set pending of PPIs

According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending Registers, GICD_ISPENDRn": "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected processor. This register holds the Set-pending bits for interrupts 0-31." Signed-off-by: Seba

[PATCH 2/2] hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn

rupt makes that interrupt pending on that CPU interface - removing a CPU interface from the target list of a pending interrupt removes the pending state of that interrupt on that CPU interface." Signed-off-by: Sebastian Huber --- hw/intc/arm_gic.c | 7 +++ 1 file changed, 7 inserti

Re: [PATCH] hw/intc/arm_gic: Fix set/clear pending of PPI/SPI

Hello Luc, thanks for having a look at the patch. On 25/07/2021 10:08, Luc Michel wrote: Hi Sebastian, On 11:49 Fri 09 Jul , Sebastian Huber wrote: According to the GICv3 specification register GICD_ISPENDR0 is Banked for each You're referring to GICv3 but actually modifying GICv2

Re: [PATCH] hw/intc/arm_gic: Fix set/clear pending of PPI/SPI

On 09/07/2021 11:49, Sebastian Huber wrote: According to the GICv3 specification register GICD_ISPENDR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case since GIC_NCPU == 8. For SPI, make the interrupt pending on all CPUs and not just

[PATCH] hw/intc/arm_gic: Fix set/clear pending of PPI/SPI

is at least present on the i.MX7D which uses an Cortex-A7MPCore. Signed-off-by: Sebastian Huber --- hw/intc/arm_gic.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index a994b1f024..8e377bac59 100644 --- a/hw/intc/arm_gi

[Bug 1277433] Re: GDB context is inconsistent after "monitor system_reset"

With this Qemu: qemu-system-arm --version QEMU emulator version 4.2.50 (v4.2.0-1276-g863d2ed582) Copyright (c) 2003-2019 Fabrice Bellard and the QEMU Project developers I still have the same issue: (gdb) info registers r0 0x0 0 r1 0x9010001 15106

[Bug 1277433] Re: GDB context is inconsistent after "monitor system_reset"

I can also build the latest Git master of Qemu if this helps. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1277433 Title: GDB context is inconsistent after "monitor system_reset" Status in QEMU:

[Qemu-devel] [PATCH] net: cadence_gem: Set initial MAC address

Set initial MAC address to the one specified by the command line. Signed-off-by: Sebastian Huber Reviewed-by: Jason Wang Reviewed-by: Peter Crosthwaite --- hw/net/cadence_gem.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 1127223

Re: [Qemu-devel] [PATCH v2] net: cadence_gem: Set initial MAC address

Ping. Attached is a rebased version. On 30/01/15 18:56, Peter Crosthwaite wrote: On Thu, Jan 29, 2015 at 9:48 PM, Sebastian Huber wrote: Set initial MAC address to the one specified by the command line. Signed-off-by: Sebastian Huber Reviewed-by: Jason Wang v2: Remove superfluous

[Qemu-devel] [PATCH v2] net: cadence_gem: Set initial MAC address

Set initial MAC address to the one specified by the command line. Signed-off-by: Sebastian Huber Reviewed-by: Jason Wang v2: Remove superfluous whitespace change. --- hw/net/cadence_gem.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c

[Qemu-devel] [PATCH] net: cadence_gem: Set initial MAC address

Set initial MAC address to the one specified by the command line. Signed-off-by: Sebastian Huber --- hw/net/cadence_gem.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index de26609..a1aa91b 100644 --- a/hw/net

Re: [Qemu-devel] [PATCH v6] target-sparc: Add and use CPU_FEATURE_CASA

Hello Fabien, On 2014-03-12 11:17, Fabien Chouteau wrote: Thanks Sebastian, I will try my first pull request :) I think Mark already did this http://lists.gnu.org/archive/html/qemu-devel/2014-03/msg02325.html ? -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178

Re: [Qemu-devel] [Qemu-trivial] [PATCH v2] hw/timer/grlib_gptimer: Avoid integer overflows

Hello, On 2014-03-02 16:56, Sebastian Huber wrote: On 03/02/2014 02:17 PM, Michael Tokarev wrote: 26.02.2014 11:53, Sebastian Huber wrote: Ping. There was another comment on this, about the first hunk, see https://lists.gnu.org/archive/html/qemu-trivial/2014-02/msg00067.html Note that the

[Qemu-devel] [PATCH v6] target-sparc: Add and use CPU_FEATURE_CASA

v5: Fix two typos. Generate an IU instead of FPU exception in case CASA is not supported by the CPU. Define CASA feature for all SPARC64 CPUs (due to the #ifndef TARGET_SPARC64 it must go into the #else branch). v6: Move CHECK_IU_FEATURE(dc, CASA); in #ifndef TARGET_SPARC64 block since SPARC64 has

[Qemu-devel] [PATCH v6] target-sparc: Add and use CPU_FEATURE_CASA

eas Färber Tested-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Signed-off-by: Sebastian Huber --- target-sparc/cpu.c |3 +- target-sparc/cpu.h |4 ++- target-sparc/helper.h |4 ++- target-sparc/ldst_helper.c | 28 ++-- t

[Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA

omic_store(&a, 3); e = 4; b = atomic_compare_exchange_strong(&a, &e, 5); assert(!b); assert(atomic_load(&a) == 3); } Tested also on a NGMP board with a LEON4 processor. Reviewed-by: Fabien Chouteau Reviewed-by: Andreas Färber Signed-off-by: Sebastian Huber v4: Fix coding style. v

Re: [Qemu-devel] [PATCH v4] target-sparc: Add and use CPU_FEATURE_CASA

es on qemu-system-sparc64 (see below for the output from current git master with the v4 patch applied): thanks for testing my patch. Can I download these ISO images somewhere so that I can try to fix my patch? -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puc

Re: [Qemu-devel] [Qemu-trivial] [PATCH v2] hw/timer/grlib_gptimer: Avoid integer overflows

On 03/02/2014 02:17 PM, Michael Tokarev wrote: 26.02.2014 11:53, Sebastian Huber wrote: Ping. There was another comment on this, about the first hunk, see https://lists.gnu.org/archive/html/qemu-trivial/2014-02/msg00067.html Note that the comment below this line mentions the +1 which is being

Re: [Qemu-devel] [PATCH v4] target-sparc: Add and use CPU_FEATURE_CASA

Hello, exists there someone who is able to commit this? On 2014-02-14 17:22, Andreas Färber wrote: Am 14.02.2014 17:06, schrieb Sebastian Huber: The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will

Re: [Qemu-devel] [PATCH v2] hw/timer/grlib_gptimer: Avoid integer overflows

Ping. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche

[Qemu-devel] [PATCH v2] hw/timer/grlib_gptimer: Avoid integer overflows

-by: Fabien Chouteau Signed-off-by: Sebastian Huber --- hw/timer/grlib_gptimer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index 74c16d6..7672d3a 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c

[Qemu-devel] [PATCH v4] target-sparc: Add and use CPU_FEATURE_CASA

; assert(atomic_load(&a) == 2); atomic_store(&a, 3); e = 4; b = atomic_compare_exchange_strong(&a, &e, 5); assert(!b); assert(atomic_load(&a) == 3); } Tested also on a NGMP board with a LEON4 processor. v4: Fix coding style. Signed-off-by: Seba

Re: [Qemu-devel] [PATCH v3] target-sparc: Add and use CPU_FEATURE_CASA

generally, independent of this patch with test case in its commit message, you may want to consider setting up tests/tcg/sparc/ for test cases and/or use qtest with accel=tcg similar to what mst did for ACPI regression testing. Ok, I will have a look at this. Is this a required step to get the pa

[Qemu-devel] [PATCH v3] target-sparc: Add and use CPU_FEATURE_CASA

; assert(atomic_load(&a) == 2); atomic_store(&a, 3); e = 4; b = atomic_compare_exchange_strong(&a, &e, 5); assert(!b); assert(atomic_load(&a) == 3); } Tested also on a NGMP board with a LEON4 processor. Signed-off-by: Sebastian Huber Reviewed-by: Fa

Re: [Qemu-devel] [PATCH v2] SPARC: Add and use CPU_FEATURE_CASA

On 2014-02-13 16:50, Fabien Chouteau wrote: On 02/13/2014 03:55 PM, Fabien Chouteau wrote: On 02/13/2014 02:00 PM, Sebastian Huber wrote: On 2014-02-13 13:01, Fabien Chouteau wrote: On 02/13/2014 10:52 AM, Sebastian Huber wrote: The LEON3 processor has support for the CASA instruction which

Re: [Qemu-devel] [PATCH v2] SPARC: Add and use CPU_FEATURE_CASA

On 2014-02-13 13:01, Fabien Chouteau wrote: On 02/13/2014 10:52 AM, Sebastian Huber wrote: The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to

[Qemu-devel] [PATCH v2] SPARC: Add and use CPU_FEATURE_CASA

b = atomic_compare_exchange_strong(&a, &e, 2); assert(b); assert(atomic_load(&a) == 2); atomic_store(&a, 3); e = 4; b = atomic_compare_exchange_strong(&a, &e, 5); assert(!b); assert(atomic_load(&a) == 3); } Signed-off-by: Sebastian Huber Reviewed-by: Fabien C

[Qemu-devel] [PATCH] hw/timer/grlib_gptimer: Avoid integer overflow

The GPTIMER uses 32-bit registers. Use a 64-bit operation to get the ptimer count, otherwise we end up with a count of 0 for GPTIMER counter values of 0x. --- hw/timer/grlib_gptimer.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/timer/grlib_gptimer.c b/hw

Re: [Qemu-devel] [Qemu-trivial] [PATCH] sparc/leon3: Initialize stack pointer

On 2014-02-06 09:57, Peter Maydell wrote: On 6 February 2014 08:40, Michael Tokarev wrote: >03.02.2014 13:18, Sebastian Huber wrote: >>A lot of real world LEON3 systems are shipped with the GRMON boot >>loader. This boot loader initializes the stack pointer with the end o

[Qemu-devel] [Bug 1277433] [NEW] GDB context is inconsistent after "monitor system_reset"

Public bug reported: After a "monitor system_reset" the GDB view to the system state differs from QEMUs processor state. Breakpoint 8, _ARMV4_Exception_interrupt () at /home/sh/rtems-4.11/c/src/../../cpukit/score/cpu/arm/arm_exc_interrupt.S:74 74 mov EXCHANGE_LR, lr (gdb) info r

Re: [Qemu-devel] [Qemu-trivial] [PATCH] sparc/leon3: Initialize stack pointer

On 2014-02-06 09:40, Michael Tokarev wrote: 03.02.2014 13:18, Sebastian Huber wrote: A lot of real world LEON3 systems are shipped with the GRMON boot loader. This boot loader initializes the stack pointer with the end of RAM address. The application can use this to detect the RAM size of a

[Qemu-devel] [PATCH v2] arm/zynq: Add software reset

Signed-off-by: Sebastian Huber Reviewed-by: Peter Crosthwaite --- hw/misc/zynq_slcr.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index e42a5b0..d1cc233 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -31,6

[Qemu-devel] [PATCH] sparc/leon3: Initialize stack pointer

A lot of real world LEON3 systems are shipped with the GRMON boot loader. This boot loader initializes the stack pointer with the end of RAM address. The application can use this to detect the RAM size of a particular board variant. Signed-off-by: Sebastian Huber --- hw/sparc/leon3.c |3

[Qemu-devel] GDB info registers vs. monitor info registers

000 y: A "monitor system_reset" triggers a call to main_cpu_reset (hw/sparc/leon3.c:51) and the CPUSPARCState is set up correctly, but via GDB I see no state change and the program executes as if nothing happened. Does this work as intended? -- Sebastian Huber, embedded brain

[Qemu-devel] [PATCH] arm/zynq: Add software reset

Signed-off-by: Sebastian Huber --- hw/misc/zynq_slcr.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index e42a5b0..433d439 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -399,6 +399,9 @@ static void

Re: [Qemu-devel] [PATCH v2] SPARC: Fix LEON3 power down instruction

Hello, maybe this patch can be qualified as trivial? http://lists.nongnu.org/archive/html/qemu-devel/2013-11/msg03488.html On 2014-01-07 19:07, Sebastian Huber wrote: Hello, would somebody mind committing this. On 12/06/2013 06:48 PM, Richard Henderson wrote: On 11/27/2013 08:50 PM

Re: [Qemu-devel] [PATCH v2] SPARC: Fix LEON3 power down instruction

Hello, would somebody mind committing this. On 12/06/2013 06:48 PM, Richard Henderson wrote: On 11/27/2013 08:50 PM, Sebastian Huber wrote: Synchronize the program counter before the power down helper call otherwise interrupts will return to the wrong context. Signed-off-by: Sebastian Huber

Re: [Qemu-devel] [PATCH v2] SPARC: Add and use CPU_FEATURE_CASA

Hello, would someone please have a look at this. On 2013-11-28 11:27, Sebastian Huber wrote: The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to

[Qemu-devel] [PATCH v2] SPARC: Add and use CPU_FEATURE_CASA

The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to generate C11 atomic operations. The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC

Re: [Qemu-devel] [PATCH] SPARC: Add and use CPU_FEATURE_CASA

Hello, On 2013-11-26 15:04, Sebastian Huber wrote: The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to generate C11 atomic operations. --- target

[Qemu-devel] [PATCH v2] SPARC: Fix LEON3 power down instruction

Synchronize the program counter before the power down helper call otherwise interrupts will return to the wrong context. Signed-off-by: Sebastian Huber --- target-sparc/translate.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc

[Qemu-devel] [PATCH] SPARC: Add and use CPU_FEATURE_CASA

The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to generate C11 atomic operations. --- target-sparc/cpu.c |3 +- target-sparc/cpu.h

[Qemu-devel] [PATCH] SPARC: Fix LEON3 power down instruction

The env->pc is not necessarily up-to-date in the helper function. Use the program counter of the disassembly context instead. Signed-off-by: Sebastian Huber --- target-sparc/helper.c|6 +++--- target-sparc/helper.h|2 +- target-sparc/translate.c |3 ++- 3 files changed

[Qemu-devel] [PATCH] smc91c111: Fix receive starvation

In case the smc91c111 interface signals that it cannot receive more packets the packets are queued and further reception will be disabled. In case the interface is again ready to receive packets notify the upper layer. Signed-off-by: Sebastian Huber --- hw/net/smc91c111.c |1 + 1 files

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

from this Security Extensions is the VBAR. So for me the only missing Qemu feature is the VBAR if I want to use nearly the same binary on Qemu and the real hardware. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax :

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

Shouldn't this be { env->cp15.c12_vbar = (uint32_t) (value & ~0x1FUL); return 0; } ? -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-b

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

? This may avoid adding a new enum arm_features. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese

Re: [Qemu-devel] SEV and WFE instructions on ARM

Hello Peter, thanks for your suggestions. I will look at the WFI support and may send a patch for the SEV/WFE, but this will take some weeks. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41

Re: [Qemu-devel] [PATCH] arm/zynq: Add software reset

On 06/07/2013 06:19 AM, Peter Crosthwaite wrote: Hi Sebastian, I'd like to get this merged with the fix I suggested. Are you able to remake or ok if I ammend and resend your patch? I am fine with your change. My version is to restrictive. -- Sebastian Huber, embedded brains GmbH Ad

[Qemu-devel] SEV and WFE instructions on ARM

CPUs: while (1) { _CPU_SMP_lock_Acquire(&lock); ++global_counter; _CPU_SMP_lock_Release(&lock); } It seems that the SEV/WFE instructions are implemented as a nop on Qemu (see in file "target-arm/translate.c" function gen_nop_hint()). So the simulator executes the busy wait

[Qemu-devel] [Bug 1182344] Re: ARM: invalid code execution after subs instruction

Thanks a lot for your help! It is not a Qemu problem. I ported the code from a pre ARMv7 environment. In the assembler code I have this: msr spsr, r5 The GNU as translates this to: msr SPSR_fc, r5 Correct is this: msr SPSR_fsxc, r5 I fixed the assembler source and now all SPSR fields

[Qemu-devel] [Bug 1182344] Re: ARM: invalid code execution after subs instruction

If I use this idle thread volatile int sdlkfj = 0; void *_CPU_Thread_Idle_body( uintptr_t ignored ) { while ( true ) { while ( sdlkfj == 0 ) { __asm__ volatile ("wfi; nop; nop; nop"); } __asm__ volatile ("wfi; nop; nop; nop"); } } then the test program seems to run forev

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