t; Signed-off-by: Dongli Zhang
> ---
> Changed since v1:
> - Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using
> AMD64_NUM_COUNTERS (suggested by Sandipan Das).
> - Use "AMD64_NUM_COUNTERS_CORE * 2 - 1", not "MSR_F15H_PERF_CTL0 +
- Use cpuid_find_entry() instead of cpu_x86_cpuid().
> - Change has_pmu_version to pmu_version.
> - Cap num_pmu_gp_counters with MAX_GP_COUNTERS.
>
> target/i386/cpu.h | 4
> target/i386/kvm/kvm.c | 48 +++++++
> 2 files changed, 43 insertions(+), 9 deletions(-)
>
Reviewed-by: Sandipan Das
uot;kvm_enabled() && IS_AMD_CPU(env)".
>
> target/i386/cpu.c | 4
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Sandipan Das
t; Signed-off-by: Dongli Zhang
> ---
> Changed since v1:
> - Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using
> AMD64_NUM_COUNTERS (suggested by Sandipan Das).
> - Use "AMD64_NUM_COUNTERS_CORE * 2 - 1", not "MSR_F15H_P
_EDX, CPUID_7_1_EDX_AVX10 },
> .to = { FEAT_24_0_EBX, ~0ull },
> },
> +{
> +.from = { FEAT_8000_0001_ECX, CPUID_EXT3_PERFCORE },
> +.to = { FEAT_8000_0022_EAX, CPUID_8000_0022_EAX_PERFMON_V2 },
> +},
> };
>
> typedef struct X86RegisterInfo32 {
Reviewed-by: Sandipan Das
On 11/4/2024 3:10 PM, Dongli Zhang wrote:
> Since perfmon-v2, the AMD PMU supports additional registers. This update
> includes get/put functionality for these extra registers.
>
> Similar to the implementation in KVM:
>
> - MSR_CORE_PERF_GLOBAL_STATUS and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS both
>
On 11/8/2024 5:14 AM, dongli.zh...@oracle.com wrote:
> Hi Zhao,
>
>
> On 11/6/24 11:52 PM, Zhao Liu wrote:
>> (+Dapang & Zide)
>>
>> Hi Dongli,
>>
>> On Mon, Nov 04, 2024 at 01:40:17AM -0800, Dongli Zhang wrote:
>>> Date: Mon, 4 Nov 2024 01:40:17 -0800
>>> From: Dongli Zhang
>>> Subject: [PATCH
On 11/4/2024 3:10 PM, Dongli Zhang wrote:
> QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM
> and kvm_put_msrs() to restore them to KVM. However, there is no support for
> AMD PMU registers. Currently, has_pmu_version and num_pmu_gp_counters are
> initialized based on cpu
but does not provide a definition of that struct.
>
> Signed-off-by: Peter Maydell
LGTM.
Reviewed-by: Sandipan Das
> ---
> I need this to be able to do the ppc64le cross-build on my
> Ubuntu Bionic x86-64 system.
>
> risu_ppc64.c | 2 ++
> risu_reginfo_ppc64.c | 1 +
This fixes the pattern for the Deliver A Random Number (darn)
instruction to ensure that the value of the L field, which is
used to determine the type and length of the generated random
number, is never 3 which is currently reserved for future use.
Signed-off-by: Sandipan Das
---
ppc64.risu | 2
$ qemu-ppc64le -cpu power9 test
0x8c00
After:
$ qemu-ppc64le -cpu power8 test
0x8c00
$ qemu-ppc64le -cpu power9 test
0x8c80
Signed-off-by: Sandipan Das
---
linux-user/elfload.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
Use 'f' instead of 'r' as the prefix when dumping the values
of floating-point registers.
Signed-off-by: Sandipan Das
---
risu_reginfo_ppc64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index eb9c12b..
registers. This can cause
a mismatch as the addresses may vary across the master and
the apprentice instances. This is avoided by always adding
8 to the offset used for calculating the ea.
Signed-off-by: Sandipan Das
---
ppc64.risu | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
The patterns for the following instructions are added:
* Load Byte and Zero (lbz)
* Load Byte and Zero with Update (lbzu)
* Load Byte and Zero Indexed (lbzx)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Doubleword (ld)
Signed-off-by: Sandipan Das
---
ppc64.risu | 25
.
Changelog:
v2 -> Added a cover letter as requested by Peter.
Sandipan Das (3):
ppc64.risu: Add missing byte and dword loads
ppc64.risu: Fix pattern for load qword
risu_reginfo_ppc64.c: Fix register name prefix
ppc64.risu | 29 +++--
risu_reginfo_ppc64.c |
On 03/06/2018 05:09 PM, Peter Maydell wrote:
> On 6 March 2018 at 06:42, Sandipan Das wrote:
>> The patterns for the following instructions are added:
>> * Load Byte and Zero (lbz)
>> * Load Byte and Zero with Update (lbzu)
>> * Load Byte and Zero Indexed (lbzx)
&g
Use 'f' instead of 'r' as the prefix when dumping the values
of floating-point registers.
Signed-off-by: Sandipan Das
---
risu_reginfo_ppc64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index eb9c12b..
registers. This can cause
a mismatch as the addresses may vary across the master and
the apprentice instances. This is avoided by always adding
8 to the offset used for calculating the ea.
Signed-off-by: Sandipan Das
---
ppc64.risu | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
The patterns for the following instructions are added:
* Load Byte and Zero (lbz)
* Load Byte and Zero with Update (lbzu)
* Load Byte and Zero Indexed (lbzx)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Doubleword (ld)
Signed-off-by: Sandipan Das
---
ppc64.risu | 25
Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
Signed-off-by: Sandipan Das
---
v2: Add tcg_temp_free() required in gen_sraw() and gen_srad()
v3: Remove explicit checking for ISA v3.0 when setting CA32
v4: Set CA32 only when CA is being modified (as Richard suggested
Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
Signed-off-by: Sandipan Das
---
v2: Add tcg_temp_free() required in gen_sraw() and gen_srad()
v3: Remove explicit checking for ISA v3.0 when setting CA32
---
target/ppc/int_helper.c | 8
target/ppc/translate.c
On Monday 22 May 2017 12:33 PM, Nikunj A Dadhania wrote:
> Sandipan Das writes:
>
>> The patterns for the following instructions are fixed:
>> * Rotate Left Doubleword then Clear Right (rldcr[.])
>> * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
>
The patterns for the following instructions are fixed:
* Rotate Left Doubleword then Clear Right (rldcr[.])
* Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
* Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
Signed-off-by: Sandipan Das
---
ppc64.risu | 10
instructions,
the extended opcodes are incorrect and the shift field 'sha' is
absent. Also, the shift field 'sh' should be used in place of the
register field 'rb'.
Signed-off-by: Sandipan Das
---
ppc64.risu | 10 +-
1 file changed, 5 insertions(+), 5 deletions
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