Re: [Qemu-devel] On x86 MMU modes

i // [Line 11] 401c12: e8 09 01 00 00 callq 401d20 <__libc_start_main> 401c17: f4 hlt 401c18: 0f 1f 84 00 00 00 00nopl 0x0(%rax,%rax,1) 401c1f: 00 On Sun, Jun 7, 2015 at 6:34 AM, Peter Maydell wrote: > On

Re: [Qemu-devel] On x86 MMU modes

89 d1mov%rdx,%r9 401bf3: 5e pop%rsi 401bf4: 48 89 e2mov%rsp,%rdx 401bf7: 48 83 e4 f0 and$0xfff0,%rsp .. and so on On Wed, Jun 3, 2015 at 5:36 PM, Peter Maydell wrote: > On 3

Re: [Qemu-devel] On x86 MMU modes

Well, I think we can also achieve this like adding a flag in the structure of CPUTLBEntry. Am I missing something? On Wed, Jun 3, 2015 at 4:22 PM, Paolo Bonzini wrote: > > > On 03/06/2015 10:07, Sandhya Kumar wrote: > > Thanks again. One more question. > > > &g

Re: [Qemu-devel] On x86 MMU modes

, Paolo Bonzini wrote: > > > On 03/06/2015 09:41, Sandhya Kumar wrote: > > Thanks for your mail. Are these TLB modes logic specific to QEMU > > implementation for x86? > > Yes, they are specific to QEMU. > > > Asking this as I am not able to get any informatio

Re: [Qemu-devel] On x86 MMU modes

Thanks for your mail. Are these TLB modes logic specific to QEMU implementation for x86? Asking this as I am not able to get any information about seperate TLBs from Intel developer manuals On Wed, Jun 3, 2015 at 3:01 PM, Paolo Bonzini wrote: > > > On 03/06/2015 08:51, Sandhya Ku

[Qemu-devel] On x86 MMU modes

[Query on intended logic] I am trying to learn qemu's MMU emulation logic for x86 and came across H. Peter Anvin's SMAP commit (link ). I have the following doubt on the intended logic (apologies if it is trivial) As per my under