On 7/16/2025 8:20 PM, Ethan MILON wrote:
On 7/16/25 09:31, Sairaj Kodilkar wrote:
Current event logging code is broken, because of following issues
1. The code uses '|' instead of '&' to test the bit field, which causes
vIOMMU to generate overflow interrupt for
On 7/16/2025 8:48 PM, Ethan MILON wrote:
On 7/16/25 09:31, Sairaj Kodilkar wrote:
The AMD IOMMU is set up at boot time and uses PCI bus numbers + devfn
for indexing into DTE. The problem is that before the guest started,
all PCI bus numbers are 0 as no PCI discovery happened yet (BIOS or/and
On 7/16/2025 7:57 PM, Ethan MILON wrote:
Hi,
On 7/16/25 09:31, Sairaj Kodilkar wrote:
Support the writes to the status register so that guest can reset the
EventOverflow, EventLogInt, ComWaitIntr, etc bits after servicing the
respective interrupt.
Signed-off-by: Sairaj Kodilkar
Reviewed
On 7/16/2025 6:59 PM, Michael S. Tsirkin wrote:
On Wed, Jul 16, 2025 at 06:26:37PM +0530, Sairaj Kodilkar wrote:
On 7/16/2025 6:07 PM, Philippe Mathieu-Daudé wrote:
On 16/7/25 09:31, Sairaj Kodilkar wrote:
This series provides few cleanups and fixes for the amd iommu
The patches are
On 7/16/2025 6:07 PM, Philippe Mathieu-Daudé wrote:
On 16/7/25 09:31, Sairaj Kodilkar wrote:
This series provides few cleanups and fixes for the amd iommu
The patches are based on top of 56c6e249b698 (v10.0.0-rc3) and
Alejandro's
DMA remapping series [1].
56c6e249b698 is 4 month
https://github.com/AMDESE/qemu-iommu/tree/sarunkod/alej%2Bcleanup-v1
Sairaj Kodilkar (7):
hw/i386/amd_iommu: Fix MMIO register write tracing
hw/i386/amd_iommu: Remove unused and wrongly set ats_enabled field
hw/i386/amd_iommu: Move IOAPIC memory region initialization to the end
hw/i386/amd_
and lookup IOTLB entry.
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodilkar
---
hw/i386/amd_iommu.c | 51 -
hw/i386/amd_iommu.h | 5 +++--
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/hw/i386/a
-off-by: Sairaj Kodilkar
---
hw/i386/amd_iommu.c | 124 +++-
hw/i386/amd_iommu.h | 2 +-
2 files changed, 76 insertions(+), 50 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index a34062153194..33916b458611 100644
--- a/hw/i386
Support the writes to the status register so that guest can reset the
EventOverflow, EventLogInt, ComWaitIntr, etc bits after servicing the
respective interrupt.
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff
ssues, so that guest can process event log entries.
Fixes: d29a09ca68428 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 20
hw/i386/amd_iommu.h | 1 +
2 files changed, 17 insertions(+), 4
use
the mr_sys and mr_ir regions after they are fully initialized.
Fixes: 577c470f4326 ("x86_iommu/amd: Prepare for interrupt remap support")
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
di
The ats_enabled field is set using HTTUNEN, which is wrong.
Fix this by removing the field as it is never used.
Fixes: d29a09ca68428 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 2 --
hw/i386/amd_iommu.h | 1
Define separate functions to trace MMIO write accesses instead of using
`trace_amdvi_mmio_read()` for both read and write.
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git
fails to compile (GCC works ok).
Thanks
Sairaj Kodilkar
On 5/31/2025 3:00 AM, Alejandro Jimenez wrote:
Hey Sairaj,
On 5/29/25 2:16 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:46 AM, Alejandro Jimenez wrote:
On reset, restore the default address translation mode for all the
address spaces managed by the vIOMMU.
Signed-off-by: Alejandro Jimenez
On 6/12/2025 1:57 PM, Ethan MILON wrote:
Hi,
On 5/2/25 4:16 AM, Alejandro Jimenez wrote:
Caution: External email. Do not open attachments or click links, unless this
email comes from a known sender and you know the content is safe.
A guest must issue an INVALIDATE_DEVTAB_ENTRY command aft
lejandro,
While experimenting with iommu.forcedac=1, I found that above line
causes unsigned integer overflow for 64 bit IOVAs. This results in an
infinite loop.
Please add a overflow check here.
Thanks
Sairaj Kodilkar
On 6/3/2025 2:24 AM, Michael Tokarev wrote:
On 16.05.2025 13:05, Sairaj Kodilkar wrote:
Fix following two issues in the amd viommu
1. The guest fails to setup the passthrough device when for following
setup
because amd iommu enables the no DMA memory region even when guest is
using
Sairaj: Are you passing a full NVME device to the guest (i.e. a PF)? I
ask because the BDF in '-device vfio-pci,host=:44:00.0' doesn't look
like a typical VF...
Hey Alejandro,
I am passing full NVME device to the guest (not just VF).
Thanks
Sairaj
ddr_translation flag to
"false" before switching all the address spaces. Without this, the
devices will keep using IOMMU address space.
Regards
Sairaj Kodilkar
}
static void amdvi_sysbus_realize(DeviceState *dev, Error **errp)
On 5/21/2025 8:05 AM, Alejandro Jimenez wrote:
Hi Sairaj
On 5/16/25 4:07 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
Hi Alejandro,
Tested the v2, everything looks good when I boot guest with upstream
kernel. But I observed that NVME driver fails to load
On 5/16/2025 8:13 PM, Philippe Mathieu-Daudé wrote:
On 16/5/25 12:05, Sairaj Kodilkar wrote:
Commit c1f46999ef506 ("amd_iommu: Add support for pass though mode")
introduces the support for "pt" flag by enabling nodma memory when
"pt=off". This allowed VFIO de
On 5/16/2025 4:06 PM, Michael S. Tsirkin wrote:
On Fri, May 16, 2025 at 03:35:33PM +0530, Sairaj Kodilkar wrote:
Fix following two issues in the amd viommu
1. The guest fails to setup the passthrough device when for following setup
because amd iommu enables the no DMA memory region even
XTSup
feature")
Reported-by: Alejandro Jimenez
Tested-by: Tested-by: Alejandro Jimenez
Cc: Philippe Mathieu-Daudé
Cc: Joao Martins
Signed-off-by: Vasant Hegde
Signed-off-by: Sairaj Kodilkar
---
hw/i386/amd_iommu.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/i386/amd_iomm
memory region.
But this will once again cause VFIO devices to fail while registering the
notifiers with AMD IOMMU memory region.
Fixes: c1f46999ef506 ("amd_iommu: Add support for pass though mode")
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 12 ++
The guest fails to boot with xtsup=on and <= 255 vCPUs, because amd_iommu
does not enable x2apic mode.
base commit 56c6e249b6988c1b6edc2dd34ebb0f1e570a1365 (v10.0.0-rc3)
Sairaj Kodilkar (1):
hw/i386/amd_iommu: Fix device setup failure when PT is on.
Vasant Hegde (1):
hw/i386/amd_iommu: F
On 5/15/2025 3:19 AM, Alejandro Jimenez wrote:
On 5/12/25 3:00 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:46 AM, Alejandro Jimenez wrote:
- if (pte & AMDVI_DEV_TRANSLATION_VALID) {
- level = get_pte_translation_mode(pte);
- if (level
cket,id=SOCKET1,server=on,wait=off,path=qemu.mon.user \
-mon chardev=SOCKET1,mode=control \
-device vfio-pci,host=:44:00.0
Do you have any idea what might trigger this.
I see the error only when I am using emulated AMD IOMMU with passthrough
device. Regular passthrough works fine.
Regard
f the amdvi_page_walk(),
amdvi_do_translate() checks the return value of amdvi_as_to_dte().
amdvi_do_translate() returns when it encounters -AMDVI_FR_DTE_TV and
does not call amdvi_page_walk().
Regards
Sairaj Kodilkar
be introduced in follow up changes).
Signed-off-by: Alejandro Jimenez
Regards
Sairaj Kodilkar
"currently supported", as->bus_num, PCI_SLOT(as->devfn),
+ PCI_FUNC(as->devfn));
Redundant whitespace changes, please revert.
Regards
Sairaj Kodilkar
/* DTE[V]=0, address is passed untranslated */
goto out;
+} else if (dte_ret == -AMDVI_FR_DTE_TV) {
+return;
}
Hi Alejandro,
You missed to handle -AMDVI_FR_DTE_RTR_ERR.
Regards
Sairaj Kodilkar
amdvi_page_walk(as, entry, ret,
++ Philippe Mathieu-Daudé
On 5/9/2025 12:15 PM, Sairaj Kodilkar wrote:
Fix following two issues in the amd viommu
1. The guest fails to setup the passthrough device when for following setup
because amd iommu enables the no DMA memory region even when guest is
using DMA remapping mode
On 5/11/2025 11:22 PM, Michael S. Tsirkin wrote:
On Fri, May 09, 2025 at 12:15:24PM +0530, Sairaj Kodilkar wrote:
Fix following two issues in the amd viommu
1. The guest fails to setup the passthrough device when for following setup
because amd iommu enables the no DMA memory region even
t; (i.e. pass the check in memory_region_is_iommu()),
and later fail when trying to register the notifier.
Fixes: c1f46999ef506 ("amd_iommu: Add support for pass though mode")
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 12 ++--
1 file ch
From: Vasant Hegde
If vCPUs > 255 then x86 common code (x86_cpus_init()) call kvm_enable_x2apic().
But if vCPUs <= 255 then it won't call kvm_enable_x2apic().
Booting guest in x2apic mode, amd-iommu,xtsup=on and <= 255 vCPUs is
broken as it fails to call kvm_enable_x2apic().
Fix this by adding
The guest fails to boot with xtsup=on and <= 255 vCPUs, because amd_iommu
does not enable x2apic mode.
base commit 56c6e249b6988c1b6edc2dd34ebb0f1e570a1365 (v10.0.0-rc3)
Sairaj Kodilkar (1):
hw/i386/amd_iommu: Fix device setup failure when PT is on.
Vasant Hegde (1):
hw/i386/amd_iommu: F
On 4/23/2025 4:15 PM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
This series adds support for guests using the AMD vIOMMU to enable DMA
remapping for VFIO devices. In addition to the currently supported
passthrough (PT) mode, guest kernels are now able to to
--
I see that nopt (emulate IOMMU) has a huge performance.
I wonder if the DMA remapping is really useful with such performance
penalty.
Regards
Sairaj Kodilkar
, the caller no longer needs to be aware of the fact
that the value has been casted from a negative number, which reduces the
risk of writing things like (pte < 0).
I prefer the out parameter solution but let's see what other reviews say.
I think having pte as out parameter is the bett
are paths (other than emulated
device write) that calls translate(). So lets keep this patch but remove
or change the example.
Regards
Sairaj Kodilkar
to sync the dirty bitmap, or after registering a new notifier. The guest
would get IO_PAGE_FAULT events for all the regions where a mapping
doesn&#x
TV=0".
Regards
Sairaj Kodilkar
If a request requires a table walk, the walk is terminated when this
condition is encountered.
Do not assume that addresses for a device with DTE[TV]=0 are passed
through (i.e. not remapped) and instead terminate the page table walk
early.
Fixes: d29a09ca6842
r, hence mr->iommu_notify list is empty and we do not unmap
the shadow page table.
Code works fine because eventually vfio_iommu_map_notify maps
entire the address space, but we should keep the right ordering.
Regards
Sairaj Kodilkar
+}
+} else if (!as->addr_translation) {
+
ed because code will call the UNMAP notifier
even if the pte is present (which should be wrong). Could you please
explain why we are unmapping IOVAs with present pte ?
Regards
Sairaj Kodilkar
+if (as->notifier_flags & IOMMU_NOTIFIER_MAP) {
+
+/* Syn
ed because code will call the UNMAP notifier
even if the pte is present (which should be wrong). Could you please
explain why we are unmapping IOVAs with present pte ?
Regards
Sairaj Kodilkar
+if (as->notifier_flags & IOMMU_NOTIFIER_MAP) {
+
+/* Syn
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
The size of the region to invalidate depends on the S bit and address
encoded in the command. Add a helper to extract this information, which
will be used to sync shadow page tables in upcoming changes.
Signed-off-by: Alejandro Jimenez
---
hw/
gnew0 initializes addr_translation to 0. but should we explicitly
initialize it to 0 ? in order to make it more readable.
Regards
Sairaj Kodilkar
+/* Enabling DMA region */
+memory_region_set_enabled(&amdvi_as->iommu_nodma, false);
+memory_region_set_enabled(MEMORY_REGION
On 4/17/2025 9:51 PM, Alejandro Jimenez wrote:
On 4/17/25 6:19 AM, Sairaj Kodilkar wrote:
On 4/17/2025 3:47 AM, Alejandro Jimenez wrote:
On 4/16/25 8:14 AM, Sairaj Kodilkar wrote:
+
+ /* DMA address translation */
+ bool dma_remap;
I think you should use this flag in the
On 4/15/2025 11:58 PM, Alejandro Jimenez wrote:
On 4/15/25 2:38 AM, Sairaj Kodilkar wrote:
Hi Alejandro,
On 4/15/2025 1:56 AM, Alejandro Jimenez wrote:
Hi Sairaj,
I'm conflicted by the implementation of the change, so I'd like to
make sure I fully understand...
On 4/10/
On 4/17/2025 3:47 AM, Alejandro Jimenez wrote:
On 4/16/25 8:14 AM, Sairaj Kodilkar wrote:
+
+ /* DMA address translation support */
+ IOMMUNotifierFlag notifier_flags;
+ /* entry in list of Address spaces with registered notifiers */
+ QLIST_ENTRY(AMDVIAddressSpace) next
on
scenario).
[1]
https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_IOMMU.pdf
Regards
Sairaj Kodilkar
PS: Sorry If I missed something here, I haven't progressed much in the
series.
};
uint64_t amdvi_extended_feature_register(AMDVIState *s);
ces with V = 0 are not translated */
-if (!(entry[0] & AMDVI_DEV_VALID)) {
+if (dte_ret == -AMDVI_FR_DTE_V) {
+/* DTE[V]=0, address is passed untranslated */
goto out;
+} else if (dte_ret == -AMDVI_FR_DTE_TV) {
+return;
}
amdvi_page_walk(as, entry, ret,
Regards
Sairaj Kodilkar
Hi Alejandro,
On 4/15/2025 1:56 AM, Alejandro Jimenez wrote:
Hi Sairaj,
I'm conflicted by the implementation of the change, so I'd like to make
sure I fully understand...
On 4/10/25 2:44 AM, Sairaj Kodilkar wrote:
Current amd_iommu enables the iommu_nodma address
check and disabling nodma memory
region. Adding pt_supported requires additional changes and we will look
into it later.
Fixes: c1f46999ef506 ("amd_iommu: Add support for pass though mode")
Signed-off-by: Sairaj Kodilkar
---
hw/i386/amd_iommu.c | 12 ++--
1 file changed, 2
From: Vasant Hegde
If vCPUs > 255 then x86 common code (x86_cpus_init()) call kvm_enable_x2apic().
But if vCPUs <= 255 then it won't call kvm_enable_x2apic().
Booting guest in x2apic mode, amd-iommu,xtsup=on and <= 255 vCPUs is
broken as it fails to call kvm_enable_x2apic().
Fix this by adding
not enable x2apic mode.
base commit 56c6e249b6988c1b6edc2dd34ebb0f1e570a1365 (v10.0.0-rc3)
Sairaj Kodilkar (1):
hw/i386/amd_iommu: Fix device setup failure when PT is on.
Vasant Hegde (1):
hw/i386/amd_iommu: Fix xtsup when vcpus < 255
hw/i386/amd_iommu.c | 20 ++--
1 file c
base address from the IVRS table and not the one provided by
PCI capability.
Sairaj Kodilkar (2):
amd_iommu: Use correct DTE field for interrupt passthrough
amd_iommu: Use correct bitmask to set capability BAR
hw/i386/amd_iommu.c | 10 +-
hw/i386/amd_iommu.h | 2 +-
2
AMD IOMMU provides the base address of control registers through
IVRS table and PCI capability. Since this base address is of 64 bit,
use 32 bits mask (instead of 16 bits) to set BAR low and high.
Fixes: d29a09ca68 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodilkar
R
Interrupt passthrough is determine by the bits 191,190,187-184.
These bits are part of the 3rd quad word (i.e. index 2) in DTE. Hence
replace dte[3] by dte[2].
Fixes: b44159fe0 ("x86_iommu/amd: Add interrupt remap support when VAPIC is not
enabled")
Signed-off-by: Sairaj Kodilkar
R
mmu: Check APIC ID > 255 for XTSup)
Signed-off-by: Sairaj Kodilkar
Signed-off-by: Santosh Shukla
Tested-by: Phil Dennis-Jordan
---
hw/i386/amd_iommu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 13af7211e11d..af0f4d
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