[PATCH] tcg/loongarch64: Optimize immediate loading

lu32i.d rd, 0 ... Signed-off-by: Rui Wang --- tcg/loongarch64/tcg-target.c.inc | 35 +++- 1 file changed, 12 insertions(+), 23 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index d326e28740

[PATCH 2/2] target/loongarch: Fix return value of CHECK_FPE

y: Richard Henderson Signed-off-by: Rui Wang --- target/loongarch/insn_trans/trans_farith.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc index e2dec75dfb..7081fbb89b 100644 --

[PATCH 0/2] Updates emulation of float-point to v4

Regarding the patchset v3 has been merged into main line, and not approved, this patch updates to patchset v4. Link: https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg00808.html Rui Wang (2): target/loongarch: Separate the hardware flags into MMU index and PLV target/loongarch: Fix

[PATCH 1/2] target/loongarch: Separate the hardware flags into MMU index and PLV

y: Richard Henderson Signed-off-by: Rui Wang --- target/loongarch/cpu.h | 18 +- .../insn_trans/trans_privileged.c.inc | 4 ++-- target/loongarch/tlb_helper.c | 4 ++-- target/loongarch/translate.c | 5 +++

[PATCH v4 0/2] target/loongarch: Fix emulation of float-point disable exception

v4: - Separate hardware flags to mmu index and plv. - Fix return value of check fpe. Rui Wang (2): target/loongarch: Adjust the layout of hardware flags bit fields target/loongarch: Fix emulation of float-point disable exception target/loongarch/cpu.c| 2

[PATCH v4 1/2] target/loongarch: Adjust the layout of hardware flags bit fields

Suggested-by: Richard Henderson Signed-off-by: Rui Wang --- target/loongarch/cpu.h| 27 --- .../insn_trans/trans_privileged.c.inc | 4 +-- target/loongarch/tlb_helper.c | 4 +-- target/loongarch/translate.c | 7

[PATCH v4 2/2] target/loongarch: Fix emulation of float-point disable exception

We need to emulate it to generate a floating point disable exception when CSR.EUEN.FPE is zero. Signed-off-by: Rui Wang --- target/loongarch/cpu.c| 2 ++ target/loongarch/cpu.h| 2 ++ .../loongarch/insn_trans/trans_farith.c.inc | 30

[PATCH v3 2/2] target/loongarch: Fix emulation of float-point disable exception

We need to emulate it to generate a floating point disable exception when CSR.EUEN.FPE is zero. Reviewed-by: Richard Henderson Reviewed-by: Song Gao Signed-off-by: Rui Wang --- target/loongarch/cpu.c| 2 ++ target/loongarch/cpu.h| 2

[PATCH v3 1/2] target/loongarch: Adjust the layout of hardware flags bit fields

Suggested-by: Richard Henderson Reviewed-by: Song Gao Signed-off-by: Rui Wang --- target/loongarch/cpu.h | 9 - target/loongarch/insn_trans/trans_privileged.c.inc | 2 +- target/loongarch/translate.c | 6 +- 3 files changed, 14

[PATCH v3 0/2] target/loongarch: Fix emulation of float-point disable exception

v3: target/loongarch: Adjust the layout of hardware flags bit fields target/loongarch: Fix emulation of float-point disable exception target/loongarch/cpu.c| 2 ++ target/loongarch/cpu.h| 11 +- .../loongarch/insn_trans/trans_farith.c.inc

[PATCH RFC] target/loongarch: Fix emulation of float-point disable exception

We need to emulate it to generate a floating point disable exception when CSR.EUEN.FPE is zero. Signed-off-by: Rui Wang --- target/loongarch/cpu.c| 2 ++ .../loongarch/insn_trans/trans_farith.c.inc | 36 +++ target/loongarch/insn_trans/trans_fcmp.c.inc

[PATCH v2] target/loongarch: Fix emulation of float-point disable exception

We need to emulate it to generate a floating point disable exception when CSR.EUEN.FPE is zero. Signed-off-by: Rui Wang --- target/loongarch/cpu.c| 2 ++ target/loongarch/cpu.h| 13 +++ .../loongarch/insn_trans/trans_farith.c.inc | 30