-
> Here's the preceeding discussion on the mailing list:
>
> https://lore.kernel.org/qemu-devel/CAFEAcA_0Hu8+G50sy0FJ2rX-=cnymlrs2nn5zy-doki...@mail.gmail.com/
>
> docs/about/deprecated.rst | 7 +++
> hw/arm/highbank.c | 2 ++
> 2 files changed, 9 insertions(+)
Acked-by: Rob Herring
Rob
this bit use the convenience pmp_is_locked() function
rather than directly checking PMP_LOCK since this function checks
mseccfg.RLB.
Signed-off-by: Rob Bradford
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index
The mvendorid/mimpid/marchid properties have the wrong amount of
whitespace ahead of them.
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3d4bd157d2..cca24b9f1f 100644
Add missing Sdtrig CSRs per the latest RISC-V Debug specification. (+ minor
whitespace fix)
Rob Bradford (2):
disas/riscv: Fix minor whitespace issues
disas/riscv: Add missing Sdtrig CSRs
disas/riscv.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
--
2.48.1
Some extra spaces made into into the RISC-V opcode data table.
Signed-off-by: Rob Bradford
---
disas/riscv.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 4075ed6bfe..305dd40ac4 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
This reflects the latest frozen version of the RISC-V Debug
specification (1.0.0-rc4) which includes the Sdtrig extension.
Signed-off-by: Rob Bradford
---
disas/riscv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 305dd40ac4
On 1/8/25 07:01, BALATON Zoltan wrote:
On Tue, 7 Jan 2025, Rob Landley wrote:
What's the alternative to -hda you suggest for that?
Can I do "./run-qemu.sh -drive file=blah.img" without the rest?
Perhaps specify all the details in the script and then optionally add
an extra
On 1/8/25 10:26, Geert Uytterhoeven wrote:
Hi Rob,
On Wed, Jan 8, 2025 at 5:23 PM Rob Landley wrote:
On 1/8/25 02:24, Geert Uytterhoeven wrote:
On Tue, Jan 7, 2025 at 11:53 PM Rob Landley wrote:
Microblaze has no /dev/?da (as in there's no device I could attach it to
even with the
On 1/8/25 08:59, Alex Bennée wrote:
Rob Landley writes:
On 1/7/25 12:05, Alex Bennée wrote:
Stafford Horne writes:
I have not used -hda before, do you have it working with other targets?
According to the qemu docs in qemu-options.hx. I see:
Use file as hard disk 0, 1, 2 or 3 image
On 1/8/25 02:24, Geert Uytterhoeven wrote:
Hi Rob,
On Tue, Jan 7, 2025 at 11:53 PM Rob Landley wrote:
Microblaze has no /dev/?da (as in there's no device I could attach it to
even with the long option, I'd have to use NBD), sh4eb has -hda is
working but it's having some endiann
rks or it doesn't.)
(And when I have to set up the long version for a nightly cron job, and
then when the test fails 6 months later and I look at it and go "huh?
salad?" that's a bad 3am digression as well. And which is more likely to
break from version skew during qemu vers
On 1/7/25 11:31, Stafford Horne wrote:
On Tue, Jan 07, 2025 at 05:56:52AM -0600, Rob Landley wrote:
On 12/31/24 19:19, Rob Landley wrote:
On 12/23/24 07:05, Stafford Horne wrote:
The kernel config looks like it should have virt block device
support, but
...
-device virtio-blk-device
On 12/31/24 19:19, Rob Landley wrote:
On 12/23/24 07:05, Stafford Horne wrote:
The kernel config looks like it should have virt block device
support, but
...
-device virtio-blk-device,drive=d0 -drive
file=${DISK},id=d0,if=none,format=qcow2
-drive file=file.img,format=raw,id=hd0 -device
but maybe I'm missing some hardware configurations.
> >
> > Hi Paolo, merry Christmas. Yes, AFAIK, there's no hardware has thread
> > level cache.
>
> Hi Zhao and Paolo,
>
> While the example looks OK to me, and makes sense. But would be curious
> to know more scenarios where I can legitimately see benefit there.
>
> I am wrestling with this point on ARM too. If I were to
> have device trees describing caches in a way that threads get their own
> private caches then this would not be possible to be
> described via device tree due to spec limitations (+CCed Rob) if I
> understood correctly.
You asked me for the opposite though, and I described how you can
share the cache. If you want a cache per thread, then you probably
want a node per thread.
Rob
x27;t working after the restore (it used to!). Nor is
microblaze's network...
Rob
it up in qemu where the
kernel can find it?
Haven't tried to get fancy with the network yet. The buildroot config is
still or1ksim...
Rob
ound line 190.)
If you provide command line args console=ttyS0 things will work.
Also console=ttyS0 is not used as all as it should be the default in QEMU.
I specify it explicitly to be consistent across architectures.
It looks like the root cause of the issue was the 'console=FIXME'.
I hope it helps.
Yup, I just had to remove workarounds for old qemu that are no longer
needed. Thanks for the help. (If you do teach qemu to exit at some
point, please let me know...)
-Stafford
Thanks,
Rob
ke sure they never have another "our
userbase refuses to move off 2.0 for a full decade" moment by holding
tightly to the control they wrested away from their users and never
giving an inch back now they've forced the issue, by making sure their
code spoils like milk and the installed base is regularly slashed and
burned, but for me that just means "use lua" or something. Yes your dev
team had trauma. So did the perl guys, who eventually gave UP forcing
their transition down an unwilling userbase's throat... But again, not
my area.)
-Stafford
Rob
On 9/16/24 02:21, Stafford Horne wrote:
On Wed, Sep 11, 2024 at 12:42:58AM -0500, Rob Landley wrote:
Grab this tarball, extract it, and ./run-qemu.sh. It's a simple
linux+initramfs image that boots to a shell prompt.
https://landley.net/bin/mkroot/latest/or1k.tgz
QEMU 7.0.0 ran that
On 11/14/24 17:33, Paolo Bonzini wrote:
On 11/15/24 00:10, Rob Landley wrote:
Seems a _bit_ awkward to do that (and potentially fail on a random new
dependency) just to delete it all again?
That's just how Make works.
Linux and busybox and so on use make, and I've never seen &
rs into the future, so
we're highly invested in seeing a converged solution in the upstream.
Thanks,
Rob
> Thanks
> Chenyi
>
> On 8/16/2024 11:02 AM, Chenyi Qiang wrote:
> > Hi Paolo,
> >
> > Hope to draw your attention. As TEE I/O would depend on shared device
n" in my devuan daedalus ("debian bookworm" fork) says version
1.0.1-5 which is nowhere near 0.59.3 or 1.5.0? QEMU built fine with it
last week, and after yet another ./configure it seems to be chugging
along building the new -rc0 tag for the moment...
Rob
gments all together.
The point of fdpic is those four segments relocate independently, so
multiple instances of the same program can share text and rodata, and
also use smaller chunks of memory for bss and data which is much easier
to come by in system without an mmu to let virtual mappings col
was wrong.
Signed-off-by: Thomas Huth
Signed-off-by: Rob Landley
Rob
On 10/24/24 00:44, Thomas Huth wrote:
On 24/10/2024 02.11, Rob Landley wrote:
I use it, and ship system images for it:
https://landley.net/bin/mkroot/latest/sh4eb.tgz
Oh, that's interesting, I've been told that the r2d machine does not
work in big endian mode:
https://lore.
On 10/23/24 19:11, Rob Landley wrote:
There was a big-endian issue breaking r2d last year, but it also broke
big endian mips and some other targets too, and it got fixed. The binary
I built a few months ago was working fine for me with vanilla qemu git
source? (I don't _think_ I had
oader on an mmu kernel, which is useful
for testing j-core userspace under qemu.
Rob
l
on reset.
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bda754b01..af602e3caf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -997,6 +997,7 @@ static void riscv_cpu_reset_hold(O
27;s still broken in current tip of tree.
Rebuilding the image with current linux-git doesn't seem to make a difference?
Either way I get serial output with old qemu and don't with current qemu.
Rob
P.S. Reproduction sequence for the tarball available upon request, kernel config
is in
From: Balaji Ravikumar
Add disassembly support for these instructions from Zawrs:
* wrs.sto
* wrs.nto
Signed-off-by: Balaji Ravikumar
Signed-off-by: Rob Bradford
---
disas/riscv.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 05b663ebfe
From: Balaji Ravikumar
Add disassembly support for these instructions from Zawrs:
* wrs.sto
* wrs.nto
Signed-off-by: Balaji Ravikumar
Signed-off-by: Rob Bradford
---
disas/riscv.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 90d6b26de9
This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.
Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.
Signed-off-by: Rob Bradford
Reviewed-by: Andrew Jone
This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
Expose the newly added extensions to the guest and allow their control
through the CPU properties.
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8d3ec74a1c..604baf53c8 100644
--- a/target
Following the pattern for 'M' and Zmmul check if either the 'A'
extension is enabled or the appropriate split extension for the
instruction.
Signed-off-by: Rob Bradford
---
target/riscv/insn_trans/trans_rva.c.inc | 56 +++--
1 file changed, 34 inserti
These extensions represent the atomic operations from A (Zaamo) and the
Load-Reserved/Store-Conditional operations from A (Zalrsc)
Signed-off-by: Rob Bradford
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu_cfg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv
ility enabling the
A instruction does not enable these two extensions - future hardware may
choose to advertise support for A and both these extensions for maximum
software support.
This patch is based off riscv-to-apply.next due to conflicts with
existing patches.
Cheers,
Rob
[1] - https://gi
These extensions represent the atomic operations from A (Zaamo) and the
Load-Reserved/Store-Conditional operations from A (Zalrsc)
Signed-off-by: Rob Bradford
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 5 +
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 7 insertions
ibility enabling the
A instruction does not enable these two extensions - future hardware may
choose to advertise support for A and both these extensions for maximum
software support.
This patch is based off riscv-to-apply.next due to conflicts with
existing patches.
Cheers,
Rob
[1] - https://gi
Following the pattern for 'M' and Zmmul check if either the 'A'
extension is enabled or the appropriate split extension for the
instruction.
Signed-off-by: Rob Bradford
---
target/riscv/insn_trans/trans_rva.c.inc | 56 +++--
1 file changed, 34 inserti
On Thu, 2024-01-18 at 16:49 -0300, Daniel Henrique Barboza wrote:
>
>
> On 1/15/24 13:25, Rob Bradford wrote:
> > Following the pattern for 'M' and Zmmul check if either the 'A'
> > extension is enabled or the appropriate split extension for the
Following the pattern for 'M' and Zmmul check if either the 'A'
extension is enabled or the appropriate split extension for the
instruction.
Also remove the assumption that only checking for 64-bit systems is
required for the double word variants.
Signed-off-by: Rob Bradfor
These extensions represent the atomic operations from A (Zaamo) and the
Load-Reserved/Store-Conditional operations from A (Zalrsc)
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 5 +
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b
ibility enabling the
A instruction does not enable these two extensions - future hardware may
choose to advertise support for A and both these extensions for maximum
software support.
This patch is based off riscv-to-apply.next due to conflicts with
existing patches.
Cheers,
Rob
[1] - https://gi
On Fri, 2024-01-12 at 17:08 +0100, Andrew Jones wrote:
> On Thu, Jan 11, 2024 at 03:17:25PM +0000, Rob Bradford wrote:
> > + Ved
> >
> > On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote:
> > > On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote:
> &g
g. Once 1.0 is frozen then
the presence of Sdtrig isa string would indicate 1.0 trigger support is
available.
According to JIRA - https://jira.riscv.org/browse/RVS-981 the debug
specification should freeze this month.
How about considering this as a solution:
- Add a new x-sdtrig option that defaults to false
- Deprecate debug option - but retain it with default on
- Add warning if triggers are used and x-sdtrig is not enabled
- Update the trigger implementation to match frozen spec
There is potentially a chance that some use cases will be broken but I
don't think triggers are being widely use - the SBI support only just
got merged:
https://github.com/riscv-software-src/opensbi/commit/97f234f15c9657c6ec69fa6ed745be8107bf6ae2
Hope this is helpful,
Rob
Add the infrastructure for the 'B' extension which is the union of the
Zba, Zbb and Zbs instructions.
Signed-off-by: Rob Bradford
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 5 +++--
target/riscv/cpu.h | 1 +
target/ris
in QEMU this extension is not
enabled by default in any cpu.
Cheers,
Rob
[1] - https://github.com/riscv/riscv-b
Changes since V1:
- Rebased on master after latest riscv updates
- All patches have R-B tags
- Array formatting fix to make future diffs clean (Daniel)
- Dropped enabling for max CPU
If the B extension is enabled warn if the user has disabled any of the
required extensions that are part of the 'B' extension. Conversely
enable the extensions that make up the 'B' extension if it is enabled.
Signed-off-by: Rob Bradford
Reviewed-by: Daniel Henrique Barboza
On Thu, 2024-01-11 at 11:53 -0300, Daniel Henrique Barboza wrote:
>
>
> On 1/11/24 10:02, Andrew Jones wrote:
> > On Wed, Jan 10, 2024 at 03:32:21PM -0300, Daniel Henrique Barboza
> > wrote:
> > >
> > >
> > > On 1/9/24 14:07, Rob Bra
+ Ved
On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote:
> On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote:
> > On Tue, Jan 09, 2024 at 05:07:35PM +, Rob Bradford wrote:
> > > Add the infrastructure for the 'B' extension which is the union
> &g
Add requirement that 'A' is enabled for all atomic instructions that
lack the check. This makes the 64-bit versions consistent with the
32-bit versions in the same file.
Signed-off-by: Rob Bradford
---
target/riscv/insn_trans/trans_rva.c.inc | 11 +++
1 file changed, 11
Add the infrastructure for the 'B' extension which is the union of the
Zba, Zbb and Zbs instructions.
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 5 +++--
target/riscv/cpu.h | 1 +
target/riscv/tcg/tcg-cpu.c | 1 +
3 files changed, 5 insertions(+), 2 deletion
If the B extension is enabled warn if the user has disabled any of the
required extensions that are part of the 'B' extension. Conversely
enable the extensions that make up the 'B' extension if it is enabled.
Signed-off-by: Rob Bradford
---
target/risc
o on in QEMU this extension is not
enabled by default in any cpu other than the 'max' variant.
Cheers,
Rob
[1] - https://github.com/riscv/riscv-b
[2] -
https://patchew.org/QEMU/20231218125334.37184-1-dbarb...@ventanamicro.com/20231218125334.37184-16-dbarb...@ventanamicro.com
Signed-off-by: Rob Bradford
---
target/riscv/tcg/tcg-cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f10871d352..9705daec93 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -999,7
Hi Alistair,
Thanks for providing some feedback - responses below:
On Mon, 2023-12-18 at 12:54 +1000, Alistair Francis wrote:
> On Fri, Dec 8, 2023 at 1:40 AM Rob Bradford
> wrote:
> >
> > From: Weiwei Li
> >
> > Add support for amocas.w/d/q instructions whic
From: Weiwei Li
Add support for amocas.w/d/q instructions which are part of the ratified
Zacas extension: https://github.com/riscv/riscv-zacas
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 2 +
target
Signed-off-by: Rob Bradford
---
disas/riscv.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index e9458e574b..8a546d5ea5 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -903,6 +903,9 @@ typedef enum {
rv_op_vwsll_vv = 872,
rv_op_vwsll_vx
iscv-software-src/riscv-tests/pull/492
Rob Bradford (1):
disas/riscv: Add amocas.[w,d,q] instructions
Weiwei Li (1):
target/riscv: Add support for Zacas extension
disas/riscv.c | 9 ++
target/riscv/cpu.c | 2 +
target/riscv/cpu_c
On Mon, 2023-10-23 at 12:02 +1000, Alistair Francis wrote:
> On Thu, Oct 19, 2023 at 1:45 AM Rob Bradford
> wrote:
> >
> > Using a mask instead of the number of PMU devices supports the
> > accurate
> > emulation of platforms that have a discontinuous set of PMU
&
e order on the command line determines which takes
precedence (later overwriting earlier.)
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 40 +-
target/riscv/cpu_cfg.h | 2 +-
target/riscv/machine.c | 2 +-
target/riscv/pmu.c | 15 +++
This has been replaced by a "pmu-mask" property that provides much more
flexibility.
Signed-off-by: Rob Bradford
Acked-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Atish Patra
---
docs/about/deprecated.rst | 12
1 file changed, 12 insertions(+)
diff --
During the FDT generation use the existing mask containing the enabled
counters rather then generating a new one. Using the existing mask will
support the use of discontinuous counters.
Signed-off-by: Rob Bradford
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Atish Patra
More closely follow the QEMU style by returning an Error and propagating
it there is an error relating to the PMU setup.
Further simplify the function by removing the num_counters parameter as
this is available from the passed in cpu pointer.
Signed-off-by: Rob Bradford
Reviewed-by: Alistair
Check the PMU available bitmask when checking if a counter is valid
rather than comparing the index against the number of PMUs.
Signed-off-by: Rob Bradford
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Atish Patra
---
target/riscv/csr.c | 5 +++--
1 file changed, 3
f MAKE_32BIT_MASK()
v2:
* Use cfg.pmu_mask wherever cfg.pmu_num was used previously
* Deprecate pmu_num property (warning, comment & updated documentation)
* Override default pmu_mask value iff pmu_num changed from default
Rob Bradford (5):
target/riscv: Propagate error from PMU setup
targe
This has been replaced by a "pmu-mask" property that provides much more
flexibility.
Signed-off-by: Rob Bradford
Acked-by: LIU Zhiwei
---
docs/about/deprecated.rst | 12
1 file changed, 12 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated
A 32-bit mask can be trivially created using the 64-bit macro so make
use of that instead.
Signed-off-by: Rob Bradford
Reviewed-by: Alistair Francis
---
target/riscv/pmu.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index
More closely follow the QEMU style by returning an Error and propagating
it there is an error relating to the PMU setup.
Further simplify the function by removing the num_counters parameter as
this is available from the passed in cpu pointer.
Signed-off-by: Rob Bradford
Reviewed-by: Alistair
Check the PMU available bitmask when checking if a counter is valid
rather than comparing the index against the number of PMUs.
Signed-off-by: Rob Bradford
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions
e property is not explicitly by the user the property default value
cannot be used so the default value must be set during the CPU object
initialisation.
If the "pmu-num" value is changed from the default then the mask will be
generated from that to support the transition to "pmu-m
dated documentation)
* Override default pmu_mask value iff pmu_num changed from default
Rob Bradford (6):
target/riscv: Propagate error from PMU setup
target/riscv: Don't assume PMU counters are continuous
target/riscv: Use existing PMU counter mask in FDT generation
target/riscv: Add &
During the FDT generation use the existing mask containing the enabled
counters rather then generating a new one. Using the existing mask will
support the use of discontinuous counters.
Signed-off-by: Rob Bradford
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c
More closely follow the QEMU style by returning an Error and propagating
it there is an error relating to the PMU setup.
Further simplify the function by removing the num_counters parameter as
this is available from the passed in cpu pointer.
Signed-off-by: Rob Bradford
Reviewed-by: Alistair
A 32-bit mask can be trivially created using the 64-bit macro so make
use of that instead.
Signed-off-by: Rob Bradford
---
target/riscv/pmu.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 9253e5f17a..052d5b1164 100644
--- a
This has been replaced by a "pmu-mask" property that provides much more
flexibility.
Signed-off-by: Rob Bradford
Acked-by: LIU Zhiwei
---
docs/about/deprecated.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated
Check the PMU available bitmask when checking if a counter is valid
rather than comparing the index against the number of PMUs.
Signed-off-by: Rob Bradford
Reviewed-by: LIU Zhiwei
---
target/riscv/csr.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c
default
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 5 +++--
target/riscv/cpu_cfg.h | 3 ++-
target/riscv/machine.c | 2 +-
target/riscv/pmu.c | 20
4 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
previously
* Deprecate pmu_num property (warning, comment & updated documentation)
* Override default pmu_mask value iff pmu_num changed from default
Rob Bradford (6):
target/riscv: Propagate error from PMU setup
target/riscv: Don't assume PMU counters are continuous
target/risc
During the FDT generation use the existing mask containing the enabled
counters rather then generating a new one. Using the existing mask will
support the use of discontinuous counters.
Signed-off-by: Rob Bradford
Reviewed-by: LIU Zhiwei
---
hw/riscv/virt.c| 2 +-
target/riscv/pmu.c | 6
On Thu, 2023-10-12 at 17:05 +0800, LIU Zhiwei wrote:
>
>
>
>
> On 2023/10/11 22:45, Rob Bradford wrote:
>
>
> >
> > Using a mask instead of the number of PMU devices supports the
> > accurate
> > emulation of platforms that
Check the PMU available bitmask when checking if a counter is valid
rather than comparing the index against the number of PMUs.
Signed-off-by: Rob Bradford
---
target/riscv/csr.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
ers though a "pmu-mask" property.
v2:
* Use cfg.pmu_mask wherever cfg.pmu_num was used previously
* Deprecate pmu_num property (warning, comment & updated documentation)
* Override default pmu_mask value iff pmu_num changed from default
Rob Bradford (6):
target/riscv: Propag
This has been replaced by a "pmu-mask" property that provides much more
flexibility.
Signed-off-by: Rob Bradford
---
docs/about/deprecated.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 8b136320e2..
During the FDT generation use the existing mask containing the enabled
counters rather then generating a new one. Using the existing mask will
support the use of discontinuous counters.
Signed-off-by: Rob Bradford
---
hw/riscv/virt.c| 2 +-
target/riscv/pmu.c | 6 +-
target/riscv/pmu.h
default
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 5 +++--
target/riscv/cpu_cfg.h | 3 ++-
target/riscv/machine.c | 2 +-
target/riscv/pmu.c | 14 ++
4 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
Add 32-bit version of mask generating macro and use it in the RISC-V PMU
code.
Signed-off-by: Rob Bradford
---
include/qemu/bitops.h | 3 +++
target/riscv/pmu.c| 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index
More closely follow the QEMU style by returning an Error and propagating
it there is an error relating to the PMU setup.
Further simplify the function by removing the num_counters parameter as
this is available from the passed in cpu pointer.
Signed-off-by: Rob Bradford
Reviewed-by: Alistair
On Mon, 2023-10-09 at 11:00 -0700, Atish Kumar Patra wrote:
> On Sun, Oct 8, 2023 at 5:58 PM Alistair Francis
> wrote:
> >
> > On Wed, Oct 4, 2023 at 7:36 PM Rob Bradford
> > wrote:
> > >
> > > Hi Atish,
> > >
> > > On Tue, 2023-1
Hi Atish,
On Tue, 2023-10-03 at 13:25 -0700, Atish Kumar Patra wrote:
> On Tue, Oct 3, 2023 at 5:51 AM Rob Bradford
> wrote:
> >
> > There is no requirement that the enabled counters in the platform
> > are
> > continuously numbered. Add a "pmu-mask" pro
Check the PMU available bitmask when checking if a counter is valid
rather than comparing the index against the number of PMUs.
Signed-off-by: Rob Bradford
---
target/riscv/csr.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
More closely follow the QEMU style by returning an Error and propagating
it there is an error relating to the PMU setup.
Further simplify the function by removing the num_counters parameter as
this is available from the passed in cpu pointer.
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c
the number of
bits set in the mask.
Signed-off-by: Rob Bradford
---
target/riscv/cpu.c | 1 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/pmu.c | 15 +--
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9d79c20c1a..
ers though a "pmu-mask" property.
Rob Bradford (3):
target/riscv: Propagate error from PMU setup
target/riscv: Support discontinuous PMU counters
target/riscv: Don't assume PMU counters are continuous
target/riscv/cpu.c | 9 -
target/riscv/cpu_cfg.h | 1 +
ta
max value to these CSRs and upon
subsequent read the appropriate number of bits for number of PMUs is
enabled and the TM bit is zero in mcountinhibit.
Signed-off-by: Rob Bradford
---
target/riscv/csr.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/riscv
must be supported." Elsewhere in the specification
it makes clear that VLEN>=ELEN.
>From inspection this new check allows:
VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8
VLEN=ELEN=32 1/2, 1/4 for SEW >=8
Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions")
On Thu, 2023-07-06 at 21:22 +0800, Weiwei Li wrote:
>
> On 2023/7/6 18:44, Rob Bradford wrote:
> > The previous check was failing with:
> >
> > ELEN = 64 SEW = 16 and LMUL = 1/8 (encoded as 5) which is a valid
> > combination.
> >
> > Fix the check to
al LMULs
of 1/2, 1/4, and 1/8 must be supported."
>From inspection this new check allows:
ELEN=64 1/2, 1/4, 1/8 (encoded as 7, 6, 5 respectfully)
ELEN=32 1/2, 1/4 (encoded as 7 and 6 respectfully)
Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions")
S
On Fri, 2023-06-02 at 23:04 +0800, Weiwei Li wrote:
>
> On 2023/6/2 20:16, Rob Bradford wrote:
> > This commit adds support for the the amocas.{w,d,q} instructions
> > behind
> > a new property to enable that instruction.
> >
> > Signed-off-by: Rob Bradford
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