[PATCH v3] Add RISCV ZALASR extension

Signed-off-by: Roan Richmond --- Ping! resending this as no movement on previous send. V3: - rebased patch onto master branch - added check for aq on Load Acquire, as pointed out by Alistair Francis - added check for rl on Store Release, as mentioned by Alistair Francis target/riscv/cpu.c

[PATCH v3] Add RISCV ZALASR extension

Signed-off-by: Roan Richmond --- V3: - rebased patch onto master branch - added check for aq on Load Acquire, as pointed out by Alistair Palmer - added check for rl on Store Release, as mentioned by Alistair Palmer target/riscv/cpu.c | 1 + target/riscv/insn32.decode

Re: [PATCH v2 1/1] Add RISCV ZALASR extension

On 11/06/2025 05:29, Alistair Francis wrote: On Tue, Jun 10, 2025 at 6:33 PM Roan Richmond wrote: This is based on version v0.8.3 of the ZALASR specification [1]. The specification is listed as in Frozen state [2]. [1]: https://github.com/riscv/riscv-zalasr/tree/v0.8.3 [2]: https://lf

Re: [PATCH v2 0/1] Add RISCV ZALASR Extension

On 11/06/2025 05:31, Alistair Francis wrote: On Tue, Jun 10, 2025 at 6:33 PM Roan Richmond wrote: Ping, resending as no responses in over week. V2: - rebased patch onto master branch - added check for RV64() for Load Double, as pointed out by Alistair Palmer. In response to Alistair

[PATCH v2 1/1] Add RISCV ZALASR extension

Signed-off-by: Roan Richmond --- target/riscv/cpu.c | 1 + target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvzalasr.c.inc | 110 +++ target/riscv/translate.c | 1 + 4 files changed, 122 insertions

[PATCH v2 0/1] Add RISCV ZALASR Extension

ng a check to ensure RL is set?" - There is no need to check if RL is set, as this is required by Spec for all Store Release instructions. Roan Richmond (1): Add RISCV ZALASR extension target/riscv/cpu.c | 1 + target/riscv/insn32.decode |

[PATCH v2] Add RISCV ZALASR extension

Signed-off-by: Roan Richmond --- V2: - rebased patch onto master branch - added check for RV64() for Load Double, as pointed out by Alistair Palmer. In response to Alistair Palmer (https://lists.gnu.org/archive/html/qemu-riscv/2025-06/msg00010.html): "Aren't you missing a check to en

[PATCH 1/1] Add RISCV ZALASR extension

Signed-off-by: Roan Richmond --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvzalasr.c.inc | 109 +++ target/riscv/translate.c

[PATCH 0/1] Add RISCV ZALASR Extension

Ping, resending as no comments in over 2 weeks. Roan Richmond (1): Add RISCV ZALASR extension target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans

[PATCH 1/1] Add RISCV ZALASR extension

Signed-off-by: Roan Richmond --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvzalasr.c.inc | 109 +++ target/riscv/translate.c

[PATCH 0/1] Add RISCV ZALASR Extension

Adds the Atomic Load-Acquire and Store-Release Extension (ZALASR). This extension is currently frozen, with no changes expected. The repository for this extension can be found: https://github.com/riscv/riscv-zalasr. Roan Richmond (1): Add RISCV ZALASR extension target/riscv/cpu.c