Hi Michael
On Mon, 4 Nov 2024 at 14:46, Michael S. Tsirkin wrote:
>
> On Tue, Sep 24, 2024 at 01:24:12PM +, Ricardo Ribalda wrote:
> > Signed-off-by: Ricardo Ribalda
>
>
> two things wrong here:
> 1. you do not describe what changed in the ASL in the commit
Signed-off-by: Ricardo Ribalda
---
tests/qtest/bios-tables-test-allowed-diff.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..f81f4e2469 100644
--- a/tests/qtest
Signed-off-by: Ricardo Ribalda
---
tests/data/acpi/x86/pc/DSDT | Bin 8527 -> 8526 bytes
tests/data/acpi/x86/pc/DSDT.acpierst| Bin 8438 -> 8437 bytes
tests/data/acpi/x86/pc/DSDT.acpihmat| Bin 9852 -> 9851 bytes
tests/data/acpi/x86/pc/DSDT.bridge
etter):
12c12
< * Length 0x3917 (14615)
---
> * Length 0x3914 (14612)
14c14
< * Checksum 0xD9
---
> * Checksum 0x09
Diff v1:
- Add assert(), Thanks Igor
Ricardo Ribalda (3):
tests/acpi: pc: allow DSDT acpi table changes
h
Mammedov
Reported-by: Mark Cave-Ayland
Fixes: 99cb2c6c7b ("hw/i386/acpi-build: Return a pre-computed _PRT table")
Closes:
https://lore.kernel.org/all/eb11c984-ebe4-4a09-9d71-1e9db7fe7...@ilande.co.uk/
Signed-off-by: Ricardo Ribalda
---
hw/i386/acpi-build.c | 3 ++-
1 file changed, 2 insert
Signed-off-by: Ricardo Ribalda
---
tests/data/acpi/x86/pc/DSDT | Bin 8527 -> 8526 bytes
tests/data/acpi/x86/pc/DSDT.acpierst| Bin 8438 -> 8437 bytes
tests/data/acpi/x86/pc/DSDT.acpihmat| Bin 9852 -> 9851 bytes
tests/data/acpi/x86/pc/DSDT.bridge
-Ayland
Fixes: 99cb2c6c7b ("hw/i386/acpi-build: Return a pre-computed _PRT table")
Closes:
https://lore.kernel.org/all/eb11c984-ebe4-4a09-9d71-1e9db7fe7...@ilande.co.uk/
Signed-off-by: Ricardo Ribalda
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Signed-off-by: Ricardo Ribalda
---
tests/qtest/bios-tables-test-allowed-diff.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..f81f4e2469 100644
--- a/tests/qtest
etter):
12c12
< * Length 0x3917 (14615)
---
> * Length 0x3914 (14612)
14c14
< * Checksum 0xD9
---
> * Checksum 0x09
Ricardo Ribalda (3):
tests/acpi: pc: allow DSDT acpi table changes
hw/i386/acpi-build: return a non-var
Hi Mark
On Sun, 22 Sept 2024 at 13:57, Mark Cave-Ayland
wrote:
>
> On 21/08/2024 15:45, Igor Mammedov wrote:
>
> > On Wed, 14 Aug 2024 11:56:08 +0000
> > Ricardo Ribalda wrote:
> >
> >> Today for x86 the _PRT() table is computed in runtime.
> >>
tic
Changelog v3->v4 Thanks Igor:
- Add missing files to tests/qtest/bios-tables-test-allowed-diff.h
Changelog v2->v3 Thanks Michael:
- Code style
- Add cover letter
Ricardo Ribalda (3):
tests/acpi: pc: allow DSDT acpi table changes
hw/i386/acpi-build: Return a pre-computed _PRT tabl
LNKS,
Zero
},
Context:
https://lore.kernel.org/virtualization/20240417145544.38d7b...@imammedo.users.ipa.redhat.com/T/#t
Signed-off-by: Ricardo Ribalda
Reviewed-by: Igor Mammedov
Reviewed-by: Richard Henderson
---
hw/i38
Signed-off-by: Ricardo Ribalda
---
tests/data/acpi/x86/pc/DSDT | Bin 6830 -> 8527 bytes
tests/data/acpi/x86/pc/DSDT.acpierst| Bin 6741 -> 8438 bytes
tests/data/acpi/x86/pc/DSDT.acpihmat| Bin 8155 -> 9852 bytes
tests/data/acpi/x86/pc/DSDT.bridge
Signed-off-by: Ricardo Ribalda
---
tests/qtest/bios-tables-test-allowed-diff.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..f81f4e2469 100644
--- a/tests/qtest
Signed-off-by: Ricardo Ribalda
---
tests/data/acpi/x86/pc/DSDT | Bin 6830 -> 8527 bytes
tests/data/acpi/x86/pc/DSDT.acpierst| Bin 6741 -> 8438 bytes
tests/data/acpi/x86/pc/DSDT.acpihmat| Bin 8155 -> 9852 bytes
tests/data/acpi/x86/pc/DSDT.bridge
Signed-off-by: Ricardo Ribalda
---
tests/qtest/bios-tables-test-allowed-diff.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..f81f4e2469 100644
--- a/tests/qtest
LNKS,
Zero
},
Context:
https://lore.kernel.org/virtualization/20240417145544.38d7b...@imammedo.users.ipa.redhat.com/T/#t
Reviewed-by: Igor Mammedov
Signed-off-by: Ricardo Ribalda
---
hw/i386/acpi-build.c | 120 --
sts/qtest/bios-tables-test-allowed-diff.h
Changelog v2->v3 Thanks Michael:
- Code style
- Add cover letter
Ricardo Ribalda (3):
tests/acpi: pc: allow DSDT acpi table changes
hw/i386/acpi-build: Return a pre-computed _PRT table
tests/acpi: pc: update golden masters for DSDT
hw/i386/acpi-b
Hi Igor
On Fri, 28 Jun 2024 at 13:25, Igor Mammedov wrote:
>
> On Fri, 7 Jun 2024 14:17:24 +0000
> Ricardo Ribalda wrote:
>
> > Signed-off-by: Ricardo Ribalda
> > ---
> > tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> > 1 file changed, 1 insertion
Ricardo Ribalda (3):
tests/acpi: pc: allow DSDT acpi table changes
hw/i386/acpi-build: Return a pre-computed _PRT table
tests/acpi: pc: update golden masters for DSDT
hw/i386/acpi-build.c | 120 ++-
tests/data/acpi/pc/DSDT | Bin 6830 -> 8
Signed-off-by: Ricardo Ribalda
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..b2c2c10cbc 100644
--- a/tests/qtest/bios-tables-test
Return (0x09)
}
Return (0x0B)
}
Method (IQCR, 1, Serialized)
{
Name (PRR0, ResourceTemplate ()
**
Signed-off-by: Ricardo Ribalda
---
tests/data/acpi/pc/DSDT | Bin 6830 -> 8527 bytes
tests/data/a
LNKS,
Zero
},
Context:
https://lore.kernel.org/virtualization/20240417145544.38d7b...@imammedo.users.ipa.redhat.com/T/#t
Signed-off-by: Ricardo Ribalda
---
hw/i386/acpi-build.c | 120 ---
1 file ch
LNKS,
Zero
},
Context:
https://lore.kernel.org/virtualization/20240417145544.38d7b...@imammedo.users.ipa.redhat.com/T/#t
Signed-off-by: Ricardo Ribalda
---
hw/i386/acpi-build.c | 118 ---
1 file ch
Signed-off-by: Ricardo Ribalda
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..b2c2c10cbc 100644
--- a/tests/qtest/bios-tables-test
Method (IQST, 1, NotSerialized)
{
If ((0x80 & Arg0))
{
Return (0x09)
}
Return (0x0B)
}
Method (IQCR, 1, Serialized)
{
Name (PRR0, ResourceTemplate ()
**
Signed-off-by: Ricardo
Friendly ping
On Wed, 17 Apr 2024 at 15:56, Ricardo Ribalda wrote:
>
> When qemu runs without kvm acceleration the ACPI executions take a great
> amount of time. If they take more than the default time (30sec), the
> ACPI calls fail and the system might not behave correctly.
>
LNKS,
Zero
},
Context:
https://lore.kernel.org/virtualization/20240417145544.38d7b...@imammedo.users.ipa.redhat.com/T/#t
Signed-off-by: Ricardo Ribalda
---
hw/i386/acpi-build.c | 118 ---
1 file ch
Hello Philippe!
On 16/08/2021 10:01, Philippe Mathieu-Daudé wrote:
On 8/16/21 2:36 PM, Jose R. Ziviani wrote:
If users try to add an isa-vga device that was already registered,
still in command line, qemu will crash:
$ qemu-system-mips64el -M pica61 -device isa-vga
RAMBlock "vga.vram" already
Hello Thomas and Gerd,
Thank you for reviewing it. Sending a v2 soon.
Thank you very much!
On 16/08/2021 02:05, Gerd Hoffmann wrote:
Hi,
+if (qemu_ram_block_by_name("vga.vram")) {
+error_report("vga.vram is already registered, ignoring this device");
+return;
+}
I
f the number of
implemented IRQs.
Signed-off-by: Ricardo Koller
---
hw/intc/arm_gicv3_cpuif.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 3e0641aff9..a032d505f5 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw
On terça-feira, 15 de junho de 2021 02:09:30 -03 Gerd Hoffmann wrote:
> On Mon, Jun 14, 2021 at 10:19:27PM +, José Ricardo Ziviani wrote:
> > Hello Gerd,
> >
> > On sexta-feira, 11 de junho de 2021 10:03:21 -03 Gerd Hoffmann wrote:
> > > Hi,
> > >
&
N¬Æ¦º[b¥ªíë,j¢Â ú+«g{Oj»vëß:ëâè4f
íz{S©ì}êÄÊ x*º^vâÖà¨×§µ<©z×±·úej)Ü
ªìz
signature.asc
Description: This is a digitally signed message part.
host.
[1] https://patchwork.ozlabs.org/patch/582756/
Signed-off-by: Ricardo Jesus
---
linux-user/main.c| 8 +++
linux-user/qemu.h| 1 +
linux-user/syscall.c | 138 +++
3 files changed, 136 insertions(+), 11 deletions(-)
diff --git a/linux
ualization type: para
L1d cache: 32K
L1i cache: 32K
NUMA node0 CPU(s): 0-15
Note: it's also possible to simulate SMT in TCG single threaded mode.
Signed-off-by: Jose Ricardo Ziviani
---
hw/ppc/spapr.c | 5 -
target/ppc/exc
Some machine based on AArch64 can have its main memory over 4GBs. With
the current path, these machines can support "-kernel" in qemu.
Note that, currently, none of the QEMU machines have their main memory over
4GBs.
Signed-off-by: Ricardo Perez Blanco
---
hw/arm/b
Hi Peter,
AFAIK, there is no board in QEMU that has its memory over 4GiB, however, we are
working in some prototypes and proof of concepts of boards with memory over
4GiB.
Kind regards,
Ricardo
> -Original Message-
> From: Peter Maydell
> Sent: Monday, November 26, 2018 9:3
Some machine based on AArch64 can have its main memory over 4GBs. With
the current path, these machines can support "-kernel" in qemu
Signed-off-by: Ricardo Perez Blanco
---
hw/arm/boot.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/arm/boot.
-system-ppc64: Error -22 while loading VM state
$
Signed-off-by: Jose Ricardo Ziviani
---
migration/savevm.c | 4 +++-
vl.c | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/migration/savevm.c b/migration/savevm.c
index 13e51f0e34..9692577318 100644
--- a/migr
From: Jose Ricardo Ziviani
We need to set cs->halted to 1 before calling ppc_set_compat. The reason
is that ppc_set_compat kicks up the new thread created to manage the
hotplugged KVM virtual CPU and the code drives directly to KVM_RUN
ioctl. When cs->halted is 1, the code:
int kvm_cp
4096 \
-smp 4,maxcpus=8,sockets=1,cores=2,threads=4 \
-display none -nographic \
-drive file=disk1.qcow2,format=qcow2
...
(qemu) device_add host-spapr-cpu-core,core-id=4
[no interaction is possible after it, only SIGKILL to take the terminal
back]
Signed-off-by: Jose Ricardo Ziviani
---
> -Original Message-
> From: Dr. David Alan Gilbert [mailto:dgilb...@redhat.com]
> Sent: Friday, June 29, 2018 2:17 PM
> To: Markus Armbruster
> Cc: Perez Blanco, Ricardo (Nokia - BE/Antwerp)
> ; Andreas Färber ;
> Dongli Zhang ; qemu-devel de...@nongnu.org>
&g
Thanks for the comments! Replying inline.
> -Original Message-
> From: Eric Blake [mailto:ebl...@redhat.com]
> Sent: Friday, June 1, 2018 6:01 PM
> To: Perez Blanco, Ricardo (Nokia - BE/Antwerp)
>
> Cc: Dr. David Alan Gilbert ; Markus Armbruster
> ; Andreas F
> -Original Message-
> From: Andreas Färber [mailto:afaer...@suse.de]
> Sent: Friday, June 8, 2018 6:20 PM
> To: Dr. David Alan Gilbert
> Cc: Perez Blanco, Ricardo (Nokia - BE/Antwerp)
> ; Eric Blake ;
> Markus Armbruster ; qemu-devel de...@nongnu.org>
> S
nsn group.
>
> Reported-by: Ricardo Ribalda Delgado
> Signed-off-by: Richard Henderson
> ---
> target/i386/translate.c | 25 -
> 1 file changed, 8 insertions(+), 17 deletions(-)
>
> diff --git a/target/i386/translate.c b/target/i386/translate.c
> i
For debugging purposes it is very useful to:
- See the description of the field. This information is already filled
in but not shown in "qom-list" command.
- Display value of the field.
Signed-off-by: Ricardo Perez Blanco
---
hmp.c | 13 +++--
qapi/misc
Hi,
As David mentioned and after using it for a while in my own project, I found
very useful printing the values for these common types.
I will summarize your comments and send a new patch.
Kind regards,
Ricardo Perez Blanco
-Original Message-
From: Dr. David Alan Gilbert
Hi,
A new patch (to be rebase on top of my previous one).
From 77f7217c07d5e3892f26082f220954678eb375b3 Mon Sep 17 00:00:00 2001
From: Ricardo Perez Blanco
Date: Mon, 16 Apr 2018 13:51:42 +0200
Subject: [PATCH] [PATCHv2] Show values and description when using "qom-list"
For
Dear all,
Here you can find my first contribution to qemu. Please, do not hesitate to do
any kind of remark.
Based on ac4ba87ae0738d7a77708f8ce31ae2378ab99654
Kind regards,
Ricardo Perez Blanco
>From 65df20cef2846d764a8a821574f5f3643391aac5 Mon Sep 17 00:00:00 2001
From: Ricardo Perez Bla
rd
Signed-off-by: Jose Ricardo Ziviani
---
accel/kvm/kvm-all.c | 4
1 file changed, 4 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 071f4f57c0..f290f487a5 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -812,10 +812,6 @@ static void kvm_mem_ioe
This reverts commit 4fe6d78b2e241f41208dfb07605aace4becfc747.
As reported
http://lists.nongnu.org/archive/html/qemu-devel/2018-01/msg05457.html
The referred commit is causing regression issues in virtio.
Signed-off-by: Jose Ricardo Ziviani
Reported-by: Anton Blanchard
---
accel/kvm/kvm-all.c
Jose Ricardo Ziviani
---
hw/ppc/spapr.c | 10 ++
target/ppc/kvm.c | 5 +
target/ppc/kvm_ppc.h | 6 ++
3 files changed, 21 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d1acfe8858..aed4d25fc4 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2261,12 +22
ports it displays an
error message and quits:
qemu-system-ppc64: KVM does not support 8 threads/core.
Available VSMT modes: 4 2 1.
Jose Ricardo Ziviani (2):
ppc: Change Power9 compat table to support at most 8 threads/core
ppc: spapr: Check if thread argument is supported by host KVM
h
tplug.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/compat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index ad8f93c064..d1770cdc6f 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -73,7 +73,7 @@ static const Compa
=0xc00d30ac thread_id=80200
CPU #4: nip=0xc00d30ac thread_id=80201
CPU #5: nip=0xc00d30ac thread_id=80202
CPU #6: nip=0xc00d30ac thread_id=80203
CPU #7: nip=0xc00d30ac thread_id=80204
This patch is based on ppc-for-2.12
Jose Ricardo Ziviani (1
ower9 guests to have 8 threads/core
if desired.
Reported-by: Satheesh Rajendran
Signed-off-by: Jose Ricardo Ziviani
---
hw/ppc/spapr.c | 14 +-
hw/ppc/trace-events | 1 +
target/ppc/kvm.c | 5 +
target/ppc/kvm_ppc.h | 6 ++
4 files changed, 25 insertions(
. (Google
is not my friend today)
I might work on implementing some of those and I do not want to step
into anyones foot, or redo work.
Thanks!
--
Ricardo Ribalda
out, "blsfill %ld (0x%lx)\n",ret, ret);
ret = test_blsic(op1);
fprintf(stdout, "blsic %ld (0x%lx)\n",ret, ret);
ret = test_t1mskc(op1);
fprintf(stdout, "t1mskc %ld (0x%lx)\n",ret, ret);
ret = test_tzmsk(op1);
fprintf(stdout, "tzmsk %ld (0x%lx)\n",ret, ret);
uot;blmsk %ld (0x%lx)\n",ret, ret);
ret = test_andn(op1,op2);
fprintf(stdout, "andn %ld (0x%lx)\n",ret, ret);
ret = test_tzcnt(op1);
fprintf(stdout, "tzcnt %ld (0x%lx)\n",ret, ret);
ret = test_bextr(op1, op2, op3);
fprintf(stdout, "bextr %ld (0x%lx)\n",ret, ret);
retq
93a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1)
The test showed than -mbmi version behaved differently than the
-march native version.
Signed-off-by: Ricardo Ribalda Delgado
---
target/i386/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/
time, unify the setup of eflags for the insn group.
>
> Reported-by: Ricardo Ribalda Delgado
> Signed-off-by: Richard Henderson
> ---
> target/i386/translate.c | 26 +-
> 1 file changed, 9 insertions(+), 17 deletions(-)
>
> diff --git a/ta
nown_op;
}
+gen_op_update2_cc();
+set_cc_op(s, CC_OP_BMILGB + ot);
break;
default:
On Wed, Jul 12, 2017 at 9:12 PM, Richard Henderson wrote:
> On 07/12/2017 08:58 AM, Ricardo Ribalda Delgado wrote:
>>
>> Hi Rich
eflags for the insn group.
>
> Reported-by: Ricardo Ribalda Delgado
> Signed-off-by: Richard Henderson
> ---
> target/i386/translate.c | 25 -
> 1 file changed, 8 insertions(+), 17 deletions(-)
>
> diff --git a/target/i386/translate.c b/target/i3
n a host that does not support TBM, so the extension is
> being used. A browse through exactly one of these used only bextr. Running
> the same tests with dejagnu using qemu-x86_64 -cpu qemu64,+tbm shows zero
> failures.
>
>
> r~
--
Ricardo Ribalda
A)
+ goto unknown_op;
+b = 0x138;
+s->vex_v = (~vex3 >> 3) & 0xf;
+s->vex_l = (vex3 >> 2) & 1;
+prefixes |= pp_prefix[vex3 & 3] | PREFIX_XOP;
+}
+fprintf(stderr, "XOP end!\n");
+break;
}
/* Post-pr
hat should support bmi1
(https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#BMI1)
What am I doing wrong?
Thanks!
cc: Richard Henderson and Blue Swril, that Implemented BEXTR
--
Ricardo Ribalda
#x27;
This patch improves this error by adding a hint instead of just that
KeyError log:
$ scripts/simpletrace.py trace-events trace-68508
'qemu_mutex_locked' event is logged but is not declared in the trace
events file, try using trace-events-all instead.
Signed-off-by: Jose Ricardo Ziv
Ricardo Ziviani
---
build-all-archs| 2 +-
configure | 13 +---
risu_ppc64.c | 40 ++
risu_ppc64le.c | 40 --
risu_reginfo_ppc64.c | 193 +
risu_reginfo_ppc64.h | 28
--pattern "ADD" ppc64.risu test.bin
Signed-off-by: Jose Ricardo Ziviani
---
risugen | 6 +-
risugen_ppc64.pm | 4
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/risugen b/risugen
index 6aad626..8b20425 100755
--- a/risugen
+++ b/risugen
@@ -264,6 +26
same: only some fixes in configure and risugen.
Also, it adds a better random initialization of VSX registers.
Jose Ricardo Ziviani (4):
risugen_ppc64: Load random 128-bit data to vector registers
configure: Add initial support to PPC64 (big endian)
risugen,risugen_ppc64.pm: Add support ppc64
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 42 +++---
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 341478c..1a3cd59 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -99,6
Uses the same ppc64 source file for both BE/LE archs since they are
essentially the same thing.
Signed-off-by: Jose Ricardo Ziviani
---
configure | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/configure b/configure
index 055e6d6..dd64d8b 100755
--- a/configure
<7d2a482a> 7924cfe3
41820040 79260022
[17582052553.370599] ---[ end trace 9470442ed18ae727 ]---
As soon as we identify and fix the issue that's causing such problem
I'll re-send the referred patch to re-enable TCE.
Signed-off-by: Jose Ricardo Ziviani
CC: Bharata B Rao
---
hw/ppc/sp
se it:
trace-event qemu_mutex_lock on|off
trace-event qemu_mutex_unlock on|off
or
trace-event qemu_mutex* on|off
Signed-off-by: Jose Ricardo Ziviani
---
v2:
- removed unecessary (void*) cast
- renamed parameter name to lock instead of qemu_global_mutex
util/qemu-thread-posix.c | 5 +
util/
it:
trace-event qemu_mutex_lock on|off
trace-event qemu_mutex_unlock on|off
or
trace-event qemu_mutex* on|off
Signed-off-by: Jose Ricardo Ziviani
---
util/qemu-thread-posix.c | 5 +
util/trace-events| 4
2 files changed, 9 insertions(+)
diff --git a/util/qemu-thread-posix.c b/util/q
(0001:03:00.0:region1+0xc0, 0xbfd0008, 8)
qemu_mutex_unlock unlocked mutex 0x10905ad8
Signed-off-by: Jose Ricardo Ziviani
---
hw/vfio/common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 145f2f4..43c8e98 100644
--- a/hw/vfio/common.
memory.c:access_with_adjusted_size() in order to be under
the same lock. Today, it's done in exec.c:address_space_write_continue()
which was able to handle only 4 bytes due to a zero'ed
valid.max_access_size (see exec.c:memory_access_size()).
Signed-off-by: Jose Ricardo Ziviani
---
hw/vfio/common.c | 4
1 file
This patchset has two patches:
[1] 8-byte writes to non-mapped MMIO are broken into pairs of 4-byte writes,
this patch makes such pairs atomic.
[2] Enable 8-byte accesses in vfio_region_write and vfio_region_read.
Patches based on master.
Jose Ricardo Ziviani (2):
vfio: Set
v2:
- applied code review
This patchset include initial support to PPC64 (Big-Endian), that is pretty
much the same: only some fixes in configure and risugen.
Also, it adds a better random initialization of VSX registers.
Jose Ricardo Ziviani (3):
risugen_ppc64: Load random 128-bit data to
--pattern "ADD" ppc64.risu test.bin
Signed-off-by: Jose Ricardo Ziviani
---
risugen | 6 +-
risugen_ppc64.pm | 4
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/risugen b/risugen
index 6aad626..086173c 100755
--- a/risugen
+++ b/risugen
@@ -264,6 +26
This commit set Makefile to point to ppc64le source for both archs
(ppc64 and ppc64le) because they do the exact same thing. The
difference is in risugen and how the binary is build.
Signed-off-by: Jose Ricardo Ziviani
---
configure | 9 -
1 file changed, 4 insertions(+), 5 deletions
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 40 +---
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 341478c..45f7220 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -99,6 +99,29
Signed-off-by: Jose Ricardo Ziviani
---
risu_reginfo_ppc64le.c | 8
1 file changed, 8 deletions(-)
diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c
index e6bc0e0..a76f296 100644
--- a/risu_reginfo_ppc64le.c
+++ b/risu_reginfo_ppc64le.c
@@ -86,14 +86,6 @@ int reginfo_is_eq
This patchset include initial support to PPC64 (Big-Endian), that is pretty
much the same: only some fixes in configure and risugen.
Also, it adds a better random initialization of VSX registers.
And does some cleanup.
Jose Ricardo Ziviani (5):
risugen_ppc64: Load random 128-bit data to VSX
Because we don't support custom fpsrc value yet it's better to remove
that code.
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 4
1 file changed, 4 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 46ab7b1..4f7c709 100644
--- a/risugen_ppc6
--pattern "ADD" ppc64.risu test.bin
Signed-off-by: Jose Ricardo Ziviani
---
risugen | 6 +-
risugen_ppc64.pm | 4
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/risugen b/risugen
index 6aad626..086173c 100755
--- a/risugen
+++ b/risugen
@@ -264,6 +26
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 40 +---
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index cb75300..28b6792 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -99,6 +99,29
This commit set Makefile to point to ppc64le source for both archs
(ppc64 and ppc64le) because they do the exact same thing. The
difference is in risugen and how the binary is build.
Signed-off-by: Jose Ricardo Ziviani
---
configure | 9 -
1 file changed, 4 insertions(+), 5 deletions
Signed-off-by: Jose Ricardo Ziviani
---
test_ppc64le.s | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/test_ppc64le.s b/test_ppc64le.s
index af23ea3..4af770c 100644
--- a/test_ppc64le.s
+++ b/test_ppc64le.s
@@ -12,15 +12,15
Signed-off-by: Jose Ricardo Ziviani
---
risu_reginfo_ppc64le.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c
index 7a54eab..e6bc0e0 100644
--- a/risu_reginfo_ppc64le.c
+++ b/risu_reginfo_ppc64le.c
@@ -105,9 +105,9
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 40f3d4f..561c17b 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -75,6 +75,13 @@ sub write_add_ri
Register R1 is defined as the stack frame pointer and R13 is the thread
local storage by ABI. So, in order to let the program flows, they are
better to keep unchanged.
Signed-off-by: Jose Ricardo Ziviani
---
test_ppc64le.s | 2 --
1 file changed, 2 deletions(-)
diff --git a/test_ppc64le.s b
This patchset contains some fixes and improvements for ppc64le.
Jose Ricardo Ziviani (7):
risu_ppc64le: improve xsrqpi[x] and xsrqpxp instructions
risu_ppc64le: fix 32-bit mov immediate
risu_ppc64le: implement sign extend for small neg constants
risu_ppc64le: implement FP random data for
Two instructions are necessary but the high value should be written
first, shifted 16 bit left, and then or'ed the lower value. This commit
fixes the problem.
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --
This commit replaces the simple FP data written for tests for a
randomically generated one. This functionality stores the same data in
FP register and VSX[VRB+32] registers.
Signed-off-by: Jose Ricardo Ziviani
---
risugen_ppc64.pm | 31 +++
1 file changed, 31
New constraint added to the referred instructions in order to avoid
generation of reserved (not used today) rounding modes for floating
point operations.
Signed-off-by: Jose Ricardo Ziviani
---
ppc64.risu | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/ppc64.risu b
xssqrtqp: VSX Scalar Square Root Quad-Precision.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/fpu_helper.c | 38 +
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c
xsrqpxp: VSX Scalar Round Quad-Precision to Double-Extended Precision.
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/fpu_helper.c | 56 +
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc
implemented when round-to-odd is ready.
Jose Ricardo Ziviani (4):
ppc: implement xsrqpi[x] instruction
ppc: implement xsrqpxp instruction
ppc: implement xssqrtqp instruction
ppc: implement xssubqp instruction
target/ppc/fpu_helper.c | 188
xsrqpi[x]: VSX Scalar Round to Quad-Precision Integer
[with Inexact].
Signed-off-by: Jose Ricardo Ziviani
---
target/ppc/fpu_helper.c | 60 +
target/ppc/helper.h | 1 +
target/ppc/internal.h | 1 +
target/ppc
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