Also, leading underscores are supposed to be reserved for compiler
implementations (and there only needs to be a single trailing
underscore) so it should really be:
__CXL_Early_Discovery_TABLE_H__ -> CXL_EARLY_DISCOVERY_TABLE_H_
--
Rebecca
On 8/30/2024 12:06 PM, Michael D Kinney via groups.
roller _was_
implemented so I missed that that's not present in sbsa-ref.
--
Rebecca Cran
For the SBSA-REF machine start all APs in the powered-off state.
This reduces host CPU usage until PSCI_CPU_ON is called when the APs
are needed.
Signed-off-by: Rebecca Cran
---
hw/arm/sbsa-ref.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
Signed-off-by: Rebecca Cran
---
hw/pci/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 5cb1232e271d..dae9119bfe5f 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1697,7 +1697,7 @@ static const pci_class_desc pci_class_descriptions
Add a space in the message printed when gicr_read*/gicr_write* returns
MEMTX_ERROR in arm_gicv3_redist.c.
Signed-off-by: Rebecca Cran
---
hw/intc/arm_gicv3_redist.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
we need to apply before yours.
Yes, it's needed. Sorry, I didn't realize there was an established
process for this.
From previous patches, I see the line should be:
Based-on: 20210508201640.1045808-1-richard.hender...@linaro.org
--
Rebecca Cran
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 +++
target/arm/helper.c | 43
2 files changed, 48 insertions(+)
diff --git a/target/arm
functions.
Moved RVAE*OS entries from the tlbios to tlbirange table.
Rebecca Cran (3):
target/arm: Add support for FEAT_TLBIRANGE
target/arm: Add support for FEAT_TLBIOS
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
target/arm/cpu.h| 10 +
target/arm/cpu64.c | 1 +
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 +
target/arm/helper.c | 281
2 files changed, 286 insertions(+)
diff --git a/target/arm
Of course I realized I only have headers for version 0.2 and upstream is
now up to 2.0, so it looks like I just need to update.
--
Rebecca Cran
On 5/8/21 3:19 PM, Rebecca Cran wrote:
I noticed that after installing liburing-devel-0.2-lp152.2.1.x86_64, a
"./configure" causes s
l/fdmon-io_uring.c:305:9: error: nested extern declaration of
‘io_uring_sq_ready’ [-Werror=nested-externs]
--
Rebecca Cran
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds
TLB invalidation instructions to invalidate ranges of addresses.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 128 +++-
include/exec/exec-all.h | 46 +++
2 files changed, 171 insertions(+), 3
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 ++
target/arm/helper.c | 75
2 files changed, 80 insertions(+)
diff --git a/target/arm
Improved readability and fixed a bug in
tlb_flush_page_range_bits_by_mmuidx_async_0.
Rebecca Cran (4):
accel/tcg: Add TLB invalidation support for ranges of addresses
target/arm: Add support for FEAT_TLBIRANGE
target/arm: Add support for FEAT_TLBIOS
target/arm: set ID_AA64ISAR0.TLB to 2
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 +
target/arm/helper.c | 296
2 files changed, 301 insertions(+)
diff --git a/target/arm
: Rebecca Cran
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d9220be7c5a..957f4247010 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4742,7 +4742,7 @@ static
Hi Richard,
Could you review this patch series again please?
I've fixed several issues recently, and am interested to know if it's
ready to commit or would need further changes.
--
Rebecca Cran
On 4/14/2021 2:32 PM, Rebecca Cran wrote:
ARMv8.4 adds the mandatory FEAT_
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds
TLB invalidation instructions to invalidate ranges of addresses.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 130 +++-
include/exec/exec-all.h | 46 +++
2 files changed, 173 insertions(+), 3
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 +
target/arm/helper.c | 296
2 files changed, 301 insertions(+)
diff --git a/target/arm
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 ++
target/arm/helper.c | 75
2 files changed, 80 insertions(+)
diff --git a/target/arm
the correct value into functions which use an ARMMMUIdx.
o Fixed comments in helper.c which referred to non-existent instructions.
Testing:
o Booted Linux 5.11 - verified the previous assert failure in qemu is
resolved.
o Ran checkpatch.pl.
Rebecca Cran (4):
accel/tcg: Add TLB invalidation
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 ++
target/arm/helper.c | 75
2 files changed, 80 insertions(+)
diff --git a/target/arm
limit. checkpatch.pl now passes.
Rebecca Cran (4):
accel/tcg: Add TLB invalidation support for ranges of addresses
target/arm: Add support for FEAT_TLBIRANGE
target/arm: Add support for FEAT_TLBIOS
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
accel/tcg/cputlb.c | 130
Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds
TLB invalidation instructions to invalidate ranges of addresses.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 130 +++-
include/exec/exec-all.h | 46 +++
2 files changed, 173 insertions(+), 3
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 +
target/arm/helper.c | 294
2 files changed, 299 insertions(+)
diff --git a/target/arm
I noticed https://wiki.qemu.org/Planning is outdated: 6.0 is listed
under Planning Pages, but at the top it says 5.0 is the release that's
currently in development.
--
Rebecca Cran
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 ++
target/arm/helper.c | 75
2 files changed, 80 insertions(+)
diff --git a/target/arm
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 +
target/arm/helper.c | 294
2 files changed, 299 insertions(+)
diff --git a/target/arm
Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds
TLB invalidation instructions to invalidate ranges of addresses.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 130 +++-
include/exec/exec-all.h | 45 +++
2 files changed, 172 insertions(+), 3
bool from tlb_flush_page_bits_locked to indicate if a full
flush has been done.
o Update flush_page_range_bits_* to exit early when a full flush has
been done.
o Run tb_flush_jmp_cache in a separate loop.
o Don't check for 2 regimes for cases where we know there's only one.
Rebec
On 3/16/21 12:09 PM, Richard Henderson wrote:
On 3/16/21 9:49 AM, Rebecca Cran wrote:
+ for (page = addr; page < (addr + length); page +=
TARGET_PAGE_SIZE) {
This test means that it's impossible to flush the last page of the
address space (addr + length == 0). I think bett
On 3/16/21 9:09 AM, Richard Henderson wrote:
On 3/16/21 12:20 AM, Rebecca Cran wrote:
On 3/10/21 12:24 PM, Richard Henderson wrote:
On 3/9/21 6:29 PM, Rebecca Cran wrote:
+ uint64_t addr = (value & 0xFUL) << TARGET_PAGE_BITS;
The manual does not explicitly say, but I
flushing a range of addresses.
o Changed the API from num_pages to length.
o Removed the exception generation from tlbi_aa64_range_get_num_pages.
o The addr is no longer passed into tlbi_aa64_range_get_num_pages.
o Other changes based on feedback.
Rebecca Cran (3):
target/arm: Add support for
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 5 ++
target/arm/helper.c | 75
2 files changed, 80 insertions(+)
diff --git a/target/arm
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 135 +
include/exec/exec-all.h | 45 +++
target/arm/cpu.h| 5 +
target/arm/helper.c
On 3/10/21 12:24 PM, Richard Henderson wrote:
On 3/9/21 6:29 PM, Rebecca Cran wrote:
+ uint64_t addr = (value & 0xFUL) << TARGET_PAGE_BITS;
The manual does not explicitly say, but I'm certain that this should be
a signed address, when regime_has_2_ranges(). Oth
geaddr);
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask,
bits);
}
--
Rebecca Cran
On 3/10/21 12:24 PM, Richard Henderson wrote:
On 3/9/21 6:29 PM, Rebecca Cran wrote:
+void tlb_flush_page_range_by_mmuidx(CPUState *cpu, target_ulong addr,
+ unsigned int num_pages, uint16_t
idxmap)
I am not keen on this interface. I think you should take
On 3/10/21 12:24 PM, Richard Henderson wrote:
On 3/9/21 6:29 PM, Rebecca Cran wrote:
+void tlb_flush_page_range_by_mmuidx(CPUState *cpu, target_ulong addr,
+ unsigned int num_pages, uint16_t
idxmap)
I am not keen on this interface. I think you should take
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 22 ++
include/exec/exec-all.h | 41
target/arm/cpu.h| 5 +
target/arm/helper.c | 248
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f0a9e968c9c1..e34a6a6174fe
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 6 ++
target/arm/helper.c | 75
2 files changed, 81 insertions(+)
diff --git a/target/arm
a short-term implementation.
Testing:
o Ran scripts/checkpatch.pl: functions in exec-all.h fail,
but I think that's acceptable?
o Built all targets
o Ran test code that executed the new instructions
o Ran "make test"
Rebecca Cran (3):
target/arm: Add support for
On 3/8/21 4:11 PM, Rebecca Cran wrote:
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
I realized this only partially addresses the feedback from v1.
Specifically, it still doesn't
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c255f1bcc393..e1003fd96138
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h| 6 ++
target/arm/helper.c | 75
2 files changed, 81 insertions(+)
diff --git a/target/arm
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 67 ++
include/exec/exec-all.h | 41
target/arm/cpu.h| 5 +
target/arm/helper.c | 248
ns
o Ran "make test": a qtest-sparc repeatedly timed out,
but that's unlikely to be due to my changes.
Rebecca Cran (3):
target/arm: Add support for FEAT_TLBIRANGE
target/arm: Add support for FEAT_TLBIOS
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
acce
oject/qemu/-/blob/master/docs/devel/style.rst
--
Rebecca Cran
On 3/5/21 4:31 AM, Peter Maydell wrote:
On Tue, 16 Feb 2021 at 22:45, Rebecca Cran wrote:
Enable FEAT_SSBS for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/a
On 2/16/21 8:45 PM, Richard Henderson wrote:
On 2/16/21 2:45 PM, Rebecca Cran wrote:
Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an
optional feature in ARMv8.0, and mandatory in ARMv8.5.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h | 15 +++-
target
Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an
optional feature in ARMv8.0, and mandatory in ARMv8.5.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h | 15 +++-
target/arm/helper.c| 37
target/arm/internals.h | 6
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c255f1bcc393..f0a9e968c9c1 100644
--- a/target/arm/cpu64
Enable FEAT_SSBS for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5cf6c056c50f..88a6b183d325 100644
--- a/target/arm/cpu.c
+++ b/
in
order.
o Moved the check for SCTLR_DSSBS_32 in take_aarch32_exception.
Rebecca Cran (3):
target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CP
On 2/15/21 5:19 PM, Richard Henderson wrote:
On 2/15/21 1:58 PM, Rebecca Cran wrote:
@@ -960,6 +960,12 @@ static void cpsr_write_from_spsr_elx(CPUARMState *env,
val |= CPSR_DIT;
}
+/* Move SSBS to the correct location for CPSR */
+if (val & PSTATE_
Enable FEAT_SSBS for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5cf6c056c50f..88a6b183d325 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2206,
Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an
optional feature in ARMv8.0, and mandatory in ARMv8.5.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h | 15 +-
target/arm/helper-a64.c| 6 +++
target/arm/helper.c| 52
target
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.
Signed-off-by: Rebecca Cran
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c255f1bcc393..f0a9e968c9c1 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
Add support for FEAT_SSBS, Speculative Store Bypass Safe. SSBS is an
optional feature in ARMv8.0 and is mandatory in ARMv8.5.
Rebecca Cran (3):
target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
target/arm: S
Enable FEAT_DIT for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8ddb2556f8cf..5cf6c056c50f 100644
--- a/target/arm/cpu.c
+++ b/
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it's
implemented as a NOP.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
targe
cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.
This allows us to add support for CPSR_DIT, adding helper functions
to merge SPSR_ELx to and from CPSR.
Signed-off-by: Rebecca Cran
---
target/arm
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4.
Changes from v4 to v5:
o Addressed review feedback.
Rebecca Cran (4):
target/arm: Add support for FEAT_DIT, Data Independent Timing
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 10c51181767d..c255f1bcc393 100644
--- a/target/arm/cpu
On 2/3/21 10:19 AM, Richard Henderson wrote:
On 2/2/21 6:58 PM, Rebecca Cran wrote:
@@ -9433,8 +9448,9 @@ static void take_aarch32_exception(CPUARMState *env, int
new_mode,
* For exceptions taken to AArch32 we must clear the SS bit in both
* PSTATE and in the old-state value we
On 2/3/21 10:17 AM, Richard Henderson wrote:
On 2/2/21 6:58 PM, Rebecca Cran wrote:
if (!arm_singlestep_active(env)) {
-env->uncached_cpsr &= ~PSTATE_SS;
+env->pstate &= ~PSTATE_SS;
+} else {
+env->pstate |= PSTATE_SS;
Enable FEAT_DIT for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 40142ac141e5..c98f44624423 100644
--- a/target/arm/cpu.c
+++ b/
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5e851028c592..9a5cfd4fc632 100644
--- a/target/arm/cpu
cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.
This allows us to add support for CPSR_DIT, adding helper functions
to merge SPSR_ELx to and from CPSR.
Signed-off-by: Rebecca Cran
---
target/arm
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it's
implemented as a NOP.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
targe
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4.
Changes from v3 to v4:
o Fixed AA32 DIT/PSTATE_SS patch following review feedback.
Rebecca Cran (4):
target/arm: Add support for FEAT_DIT, Data Independent Timing
target/arm: Support AA32 DIT by
On 1/27/21 10:06 PM, Richard Henderson wrote:
On 1/27/21 6:45 PM, Rebecca Cran wrote:
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it&#
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5e851028c592..9a5cfd4fc632 100644
--- a/target/arm/cpu
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it's
implemented as a NOP.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
targe
Enable FEAT_DIT for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 40142ac141e5..c98f44624423 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2197,
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4.
Changes from v2 to v3:
o Fixed PSTATE_SS patch:
- Reverted the singlestep removal.
- Fixed saving cpsr into spsr.
o Added DIT to the max 32-bit CPU.
Rebecca Cran (4):
target/arm: Remove PSTATE_SS
cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.
Signed-off-by: Rebecca Cran
---
target/arm/helper-a64.c | 2 +-
target/arm/helper.c | 2 +-
target/arm/op_helper.c | 9 +
3 fil
On 1/22/21 2:03 PM, Richard Henderson wrote:
On 1/21/21 6:45 PM, Rebecca Cran wrote:
cpsr_write(env, spsr, mask, CPSRWriteRaw);
-if (!arm_singlestep_active(env)) {
-env->uncached_cpsr &= ~PSTATE_SS;
-}
+env->pstate &= ~PSTATE_SS;
On 1/22/21 2:06 PM, Richard Henderson wrote:
On 1/21/21 6:45 PM, Rebecca Cran wrote:
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
There is also a 32-bit
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5e851028c592..9a5cfd4fc632 100644
--- a/target/arm/cpu
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it's
implemented as a NOP.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h
cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.
Signed-off-by: Rebecca Cran
---
target/arm/helper-a64.c | 4 +---
target/arm/helper.c | 4 ++--
target/arm/op_helper.c | 9 +
3 fil
ation is incomplete.
Rebecca Cran (3):
target/arm: Remove PSTATE_SS from cpsr and move it into env->pstate.
target/arm: Add support for FEAT_DIT, Data Independent Timing
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64
CPU
target/arm/cpu.h | 12
ARMv8.4 adds the mandatory FEAT_TLBIRANGE, which provides instructions
for invalidating ranges of entries.
Signed-off-by: Rebecca Cran
---
accel/tcg/cputlb.c | 24 ++
include/exec/exec-all.h | 39 +++
target/arm/helper.c | 273
3 files changed, 336 insertions
Enable support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 649213082ff9..4b9c5887cc1c 100644
ARMv8.4 adds the mandatory FEAT_TLBIOS, which provides instructions
for TLB invalidation of entries in the Outer Shareable domain.
Signed-off-by: Rebecca Cran
---
target/arm/helper.c | 30
1 file changed, 30 insertions(+)
diff --git a/target/arm/helper.c b/target/arm
This series adds support for FEAT_TLBIOS and FEAT_TLBIRANGE, both of
which are mandatory in ARMv8.4.
Rebecca Cran (3):
target/arm: add FEAT_TLBIOS support
target/arm: add FEAT_TLBIRANGE support
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
accel/tcg/cputlb.c | 24
ething the arm
maintainers would fix?
--
Rebecca Cran
ARMv8.4-DIT -- need to move SS somewhere else.
*/
return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS);
}
--
Rebecca Cran
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic, it's implemented as a NOP.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h | 20 +-
target/arm/helper.c
This series adds support for DIT (Data Independent Timing), and then
enables it for the "max" aarch64 CPU type.
Rebecca Cran (2):
target/arm: add support for FEAT_DIT, Data Independent Timing
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64
CP
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 649213082ff9..223e0bfd22c2 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
Update containers.yml to use the $CI_REGISTRY variable as other files
such as edk2.yml do.
Signed-off-by: Rebecca Cran
---
.gitlab-ci.d/containers.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index 11d079ea5810
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