No worries, and thanks!
On Mon, Jun 24, 2024 at 3:52 PM Peter Maydell wrote:
>
> On Mon, 24 Jun 2024 at 10:12, Rayhan Faizel wrote:
> >
> > Hi,
> >
> > The patch series is still not merged.
>
> Oops, sorry about that -- not sure how it got lost. I have
>
Hi,
The patch series is still not merged.
On Thu, May 30, 2024 at 6:57 PM Peter Maydell wrote:
>
> On Sun, 19 May 2024 at 10:42, Rayhan Faizel wrote:
> >
> > All BCM2835 boards have on-board OTP memory with 66 32-bit rows. Usually,
> > its contents are accessi
, NOT bit 30 of row 30. This is
currently undocumented to my knowledge.
-- The above lock indeed applies to the private key as well.
Rayhan Faizel (3):
hw/nvram: Add BCM2835 OTP device
hw/arm: Connect OTP device to BCM2835
hw/misc: Implement mailbox properties for customer OTP and device
Replace stubbed OTP memory region with the new OTP device.
Signed-off-by: Rayhan Faizel
---
hw/arm/bcm2835_peripherals.c | 13 -
include/hw/arm/bcm2835_peripherals.h | 3 ++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw
The OTP device registers are currently stubbed. For now, the device
houses the OTP rows which will be accessed directly by other peripherals.
Signed-off-by: Rayhan Faizel
---
hw/nvram/bcm2835_otp.c | 187 +
hw/nvram/meson.build | 1 +
include
customer OTP can be locked with the magic numbers 0x 0xaffe
when running the SET_CUSTOMER_OTP mailbox command. Bit 6 of row 32 indicates
this lock, which is undocumented. The lock also applies to the device-specific
private key.
Signed-off-by: Rayhan Faizel
---
hw/arm/bcm2835_peripherals.c
Replace stubbed OTP memory region with the new OTP device.
Signed-off-by: Rayhan Faizel
---
hw/arm/bcm2835_peripherals.c | 13 -
include/hw/arm/bcm2835_peripherals.h | 3 ++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw
The OTP device registers are currently stubbed. For now, the device
houses the OTP rows which will be accessed directly by other peripherals.
Signed-off-by: Rayhan Faizel
---
hw/nvram/bcm2835_otp.c | 187 +
hw/nvram/meson.build | 1 +
include
customer OTP can be locked with the magic numbers 0x 0xaffe
when running the SET_CUSTOMER_OTP mailbox command. Bit 6 of row 32 indicates
this lock, which is undocumented. The lock also applies to the device-specific
private key.
Signed-off-by: Rayhan Faizel
---
hw/arm/bcm2835_peripherals.c
above lock indeed applies to the private key as well.
Rayhan Faizel (3):
hw/nvram: Add BCM2835 OTP device
hw/arm: Connect OTP device to BCM2835
hw/misc: Implement mailbox properties for customer OTP and device
specific private keys
hw/arm/bcm2835_peripherals.c | 15 ++-
hw/misc
None of the RPi boards have ADC on-board. In real life, an external ADC chip
is required to operate on analog signals.
Signed-off-by: Rayhan Faizel
---
docs/system/arm/raspi.rst | 1 -
1 file changed, 1 deletion(-)
diff --git a/docs/system/arm/raspi.rst b/docs/system/arm/raspi.rst
index
customer OTP can be locked with the magic numbers 0x 0xaffe
when running the SET_CUSTOMER_OTP mailbox command.
P.S I am not sure if the magic lock combo applies to the private key as well.
Signed-off-by: Rayhan Faizel
---
hw/arm/bcm2835_peripherals.c | 2 +
hw/misc
All BCM2835 boards have on-board OTP memory with 66 32-bit rows. Usually,
its contents are accessible via mailbox commands.
Rayhan Faizel (3):
hw/nvram: Add BCM2835 OTP device
hw/arm: Connect OTP device to BCM2835
hw/misc: Implement mailbox properties for customer OTP and device
The OTP device registers are currently stubbed. For now, the device
houses the OTP rows which will be accessed directly by other peripherals.
Signed-off-by: Rayhan Faizel
---
hw/nvram/bcm2835_otp.c | 187 +
hw/nvram/meson.build | 1 +
include
Signed-off-by: Rayhan Faizel
---
hw/arm/bcm2835_peripherals.c | 13 -
include/hw/arm/bcm2835_peripherals.h | 3 ++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 1695d8b453..7d735bb56c 100644
BCM2835 has three I2C controllers. All of them share the same interrupt line.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig | 1 +
hw/arm/bcm2835_peripherals.c | 45 ++--
include/hw/arm/bcm2835_peripherals.h | 4 ++-
3 files changed, 46
active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel
Reviewed-by: Peter Maydell
---
docs/system/arm/raspi.rst| 1 +
hw/i2c/Kconfig | 4 +
hw/i2c/bcm2835_i2c.c | 282 +++
hw/i2c/meson.build
[Changes in v3]
- Add SPDX license identifiers.
- Fix a few minor whitespace issues.
[Changes in v2]
- Fixed and simplified writing to status register
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/481
Signed-off-by: Rayhan Faizel
Rayhan Faizel (3):
hw/i2c: Implement Broadcom Serial
Simple testcase for validating proper operation of read and write for all
three BSC controllers.
Signed-off-by: Rayhan Faizel
Reviewed-by: Peter Maydell
---
tests/qtest/bcm2835-i2c-test.c | 115 +
tests/qtest/meson.build| 2 +-
2 files changed, 116
.
- Fix a few minor whitespace issues.
[Changes in v2]
- Fixed and simplified writing to status register
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/481
Signed-off-by: Rayhan Faizel
Rayhan Faizel (3):
hw/i2c: Implement Broadcom Serial Controller (BSC)
hw/arm: Connect BSC to BCM2835
active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel
Reviewed-by: Peter Maydell
---
docs/system/arm/raspi.rst| 1 +
hw/i2c/Kconfig | 4 +
hw/i2c/bcm2835_i2c.c | 282 +++
hw/i2c/meson.build
BCM2835 has three I2C controllers. All of them share the same interrupt line.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig | 1 +
hw/arm/bcm2835_peripherals.c | 45 ++--
include/hw/arm/bcm2835_peripherals.h | 4 ++-
3 files changed, 46
Simple testcase for validating proper operation of read and write for all
three BSC controllers.
Signed-off-by: Rayhan Faizel
Reviewed-by: Peter Maydell
---
tests/qtest/bcm2835-i2c-test.c | 115 +
tests/qtest/meson.build| 2 +-
2 files changed, 116
Simple testcase for validating proper operation of read and write for all
three BSC controllers.
Signed-off-by: Rayhan Faizel
---
tests/qtest/bcm2835-i2c-test.c | 107 +
tests/qtest/meson.build| 2 +-
2 files changed, 108 insertions(+), 1 deletion
/qemu-project/qemu/-/issues/481
Signed-off-by: Rayhan Faizel
Rayhan Faizel (3):
hw/i2c: Implement Broadcom Serial Controller (BSC)
hw/arm: Connect BSC to BCM2835 board as I2C0, I2C1 and I2C2
tests/qtest: Add testcase for BCM2835 BSC
docs/system/arm/raspi.rst| 1 +
hw/arm/Kconfig
BCM2835 has three I2C controllers. All of them share the same interrupt line.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig | 1 +
hw/arm/bcm2835_peripherals.c | 32 +---
include/hw/arm/bcm2835_peripherals.h | 3 ++-
3 files changed, 32
active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel
---
docs/system/arm/raspi.rst| 1 +
hw/i2c/Kconfig | 4 +
hw/i2c/bcm2835_i2c.c | 278 +++
hw/i2c/meson.build | 1 +
include/hw/i2c
Hi Thomas,
Do you want me to add an SPDX line to the other two commits or will just
this one suffice?
On Tue, Feb 20, 2024 at 9:45 AM Thomas Huth wrote:
> On 19/02/2024 23.59, Rayhan Faizel wrote:
> > Simple testcase for validating proper operation of read and write for all
>
This patch series implements support for the Broadcom Serial Controller used
by BCM2835 based boards for I2C.
[Changes in v2]
- Fixed and simplified writing to status register
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/481
Signed-off-by: Rayhan Faizel
Rayhan Faizel (3):
hw/i2c
BCM2835 has three I2C controllers. All of them share the same interrupt line.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig | 1 +
hw/arm/bcm2835_peripherals.c | 32 +---
include/hw/arm/bcm2835_peripherals.h | 3 ++-
3 files changed, 32
Simple testcase for validating proper operation of read and write for all
three BSC controllers.
Signed-off-by: Rayhan Faizel
---
tests/qtest/bcm2835-i2c-test.c | 105 +
tests/qtest/meson.build| 2 +-
2 files changed, 106 insertions(+), 1 deletion
active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel
---
docs/system/arm/raspi.rst| 1 +
hw/i2c/Kconfig | 4 +
hw/i2c/bcm2835_i2c.c | 274 +++
hw/i2c/meson.build | 1 +
include/hw/i2c
Simple testcase for validating proper operation of read and write for all
three BSC controllers.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/481
Signed-off-by: Rayhan Faizel
---
tests/qtest/bcm2835-i2c-test.c | 105 +
tests/qtest/meson.build
BCM2835 has three I2C controllers. All of them share the same interrupt line.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig | 1 +
hw/arm/bcm2835_peripherals.c | 32 +---
include/hw/arm/bcm2835_peripherals.h | 3 ++-
3 files changed, 32
active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel
---
docs/system/arm/raspi.rst| 1 +
hw/i2c/Kconfig | 4 +
hw/i2c/bcm2835_i2c.c | 277 +++
hw/i2c/meson.build | 1 +
include/hw/i2c
This patch series implements support for the Broadcom Serial Controller used
by BCM2835 based boards for I2C.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/481
Signed-off-by: Rayhan Faizel
Rayhan Faizel (3):
hw/i2c: Implement Broadcom Serial Controller (BSC)
hw/arm: Connect BSC to
This patch will allow the SPI controller to be accessible from BCM2835 based
boards as SPI0. SPI driver is usually disabled by default and config.txt does
not work.
Instead, dtmerge can be used to apply spi=on on a bcm2835 dtb file.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes
of transfer are supported. DMA and LoSSI modes are currently unimplemented.
Signed-off-by: Rayhan Faizel
---
docs/system/arm/raspi.rst| 2 +-
hw/ssi/Kconfig | 4 +
hw/ssi/bcm2835_spi.c
in cover letter.
[Changes in v2]
- Forgot to CC maintainers and mailing in the patch series.
- Sign off cover letter.
Signed-off-by: Rayhan Faizel
Rayhan Faizel (2):
hw/ssi: Implement BCM2835 SPI Controller
hw/arm: Connect SPI Controller to BCM2835
docs/system/arm/raspi.rst
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes
of transfer are supported. DMA and LoSSI modes are currently unimplemented.
Signed-off-by: Rayhan Faizel
---
docs/system/arm/raspi.rst| 3 +-
hw/ssi/Kconfig | 4 +
hw/ssi/bcm2835_spi.c
This patch will allow the SPI controller to be accessible from BCM2835 based
boards as SPI0. SPI driver is usually disabled by default and config.txt does
not work.
Instead, dtmerge can be used to apply spi=on on a bcm2835 dts file.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes
of transfer are supported. DMA and LoSSI modes are currently unimplemented.
Signed-off-by: Rayhan Faizel
---
docs/system/arm/raspi.rst| 3 +-
hw/ssi/Kconfig | 4 +
hw/ssi/bcm2835_spi.c
This patch series implements the SPI controller for BCM2835 boards.
Please disregard v1 and v2 as I ran into issues with email submission.
Signed-off-by: Rayhan Faizel
Rayhan Faizel (2):
hw/ssi: Implement BCM2835 SPI Controller
hw/arm: Connect SPI Controller to BCM2835
docs/system/arm
This patch series implements the SPI controller for BCM2835 boards.
[Changes in v2]
- Accidentally forgot to CC maintainers
- Signed cover letter
Signed-off-by: Rayhan Faizel
Rayhan Faizel (2):
hw/ssi: Implement BCM2835 SPI Controller
hw/arm: Connect SPI Controller to BCM2835
docs/system
This patch will allow the SPI controller to be accessible from BCM2835 based
boards as SPI0. SPI driver is usually disabled by default and config.txt does
not work.
Instead, dtmerge can be used to apply spi=on on a bcm2835 dts file.
Signed-off-by: Rayhan Faizel
---
hw/arm/Kconfig
This patch series implements the SPI controller for BCM2835 boards.
[Changes in v2]
- Accidentally forgot to CC maintainers
- Signed cover letter
Signed-off-by: Rayhan Faizel
Rayhan Faizel (2):
hw/ssi: Implement BCM2835 SPI Controller
hw/arm: Connect SPI Controller to BCM2835
docs/system
This patch creates the SPI controller for the BCM2835. Polling and interrupt
modes
of transfer are supported. DMA and LoSSI modes are currently unimplemented.
Signed-off-by: Rayhan Faizel
---
docs/system/arm/raspi.rst| 3 +-
hw/ssi/Kconfig | 4 +
hw/ssi/bcm2835_spi.c
This patch will allow the SPI controller to be accessible from BCM2835 based
boards as SPI0. SPI driver is however usually disabled by default and config.txt
does not work.
Instead, dtmerge can be used to apply spi=on on a bcm2835 dts file as a
workaround
Signed-off-by: Rayhan Faizel
---
hw
This patch series implements the SPI controller for BCM2835 boards.
Rayhan Faizel (2):
hw/ssi: Implement BCM2835 SPI Controller
hw/arm: Connect SPI Controller to BCM2835
docs/system/arm/raspi.rst| 3 +-
hw/arm/Kconfig | 1 +
hw/arm/bcm2835_peripherals.c
timer initialization to realize
[Changes in v2]
As per Peter Maydell's suggestions,
- Use generic FIFO32 implementation in place of handmade impl.
- Moved timer_init to serial init and use timer_del in reset
- Removed stray whitespaces
- Increment VMSTATE version
Signed-off-by: Rayhan F
to realize
[Changes in v2]
As per Peter Maydell's suggestions,
- Use generic FIFO32 implementation in place of handmade impl.
- Moved timer_init to serial init and use timer_del in reset
- Removed stray whitespaces
- Increment VMSTATE version
Signed-off-by: Rayhan Faizel
---
hw
ce of handmade impl.
- Moved timer_init to serial init and use timer_del in reset
- Removed stray whitespaces
- Increment VMSTATE version
Signed-off-by: Rayhan Faizel
---
hw/char/imx_serial.c | 99 +++-
include/hw/char/imx_serial.h | 18 ++-
2 files changed
receive FIFO.
Otherwise, RRDY is set when trigger level is
exceeded. The receive trigger level is 8 in newer kernel versions and 1 in
older ones.
Signed-off-by: Rayhan Faizel
---
hw/char/imx_serial.c | 116 ++-
include/hw/char/imx_serial.h | 22 ++-
2 files
/1376
Signed-off-by: Rayhan Faizel
---
target/i386/tcg/seg_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index e8d19c65fd..4c36462162 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -78,6
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