Re: [PATCH] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores

2020-08-06 Thread Randy Yates
Good! Thank you, Philippe. --Randy On 8/6/20 8:54 AM, Peter Maydell wrote: On Thu, 9 Jul 2020 at 16:23, Philippe Mathieu-Daudé wrote: The 'Cortex-A9MPCore internal peripheral' block can only be used with Cortex A5 and A9 cores. As we don't model the A5 yet, simply check the machine cpu core i

Re: [PATCH] target/arm: Allow user-mode code to write CPSR.E via MSR

2020-05-18 Thread Randy Yates
here. > > Indeed CPSR_EXEC -> CPSR_USER typo. > >> >> Otherwise, >> Reviewed-by: Richard Henderson >> >> >> r~ >> >>> >>> (The recommended way to change CPSR.E is to use the 'SETEND' >>> instruction, which we

Re: QEMU Development Questions

2020-04-17 Thread Randy Yates
Thanks for the answers I've received so far - much appreciated. Is there a standard way to define your own custom coprocessor CP15 registers? Randy 1 Randy Yates, DSP/Embedded Firmware Developer Digital Signal Labs

QEMU Development Questions

2020-04-17 Thread Randy Yates
ntion of highmem/lowmem. What does this mean? (b) Throughout there are "PL" devices, e.g., PL111. What does "PL" mean? 3 Conclusion That's all for now - thanks for all help/suggestions/pointers/etc.