Re: [PATCH v4 1/2] hw/pci-host/gt64120: Fix endianness handling

Hi , Thank you for reviewing the previous versions of this patch. I've incorporated all the feedback in v4: 1. set .min_access_size=4 2. Simplified swapping to bswap32 only Note: I realized after sending v4 that the commit message still referenced the old size-specific swap approach -"Implement s

Re: [PATCH] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

M Philippe Mathieu-Daudé wrote: > On 29/3/25 12:30, Rakesh J wrote: > > Thanks for feedback on [PATCH v1]! > > > > I've posted v2 incorporating the suggestions:ve posted v2 incorporating > > your suggestions > > > > Paolo: You pointed out the size is

Re: [PATCH v2] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

On Sat, Mar 29, 2025 at 5:18 PM Philippe Mathieu-Daudé wrote: > Hi Rakesh, > > On 29/3/25 01:49, rakeshj wrote: > > The GT-64120 PCI controller requires special handling where: > > 1. Host bridge (device 0) must use native endianness > > 2. Other devices follow MByteSwap bit in GT_PCI0_CMD > > >

Re: [PATCH v2] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

Thanks, BALATON I looked into PCI_BUS_NUM and PCI_SLOT from include/hw/pci/pci.h (L15-24): - PCI_BUS_NUM(x) (((x) >> 8) & 0xff)) --> bits 15-8. - PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)), which don’t align properly with the 32-bit phb->config_reg layout used in your GT-64120 . Since these macros ar

Re: [PATCH] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling

Thanks for feedback on [PATCH v1]! I've posted v2 incorporating the suggestions:ve posted v2 incorporating your suggestions Paolo: You pointed out the size issue with .min_access_size = 1 and .max_access_size = 4, where bswap32 was wrong for 2-byte accesses. I’ve fixed this with size-appropriate