ve or downgrade more references to N extension
(#674)")
commit b6cade07034d ("Remove N extension chapter for now")
Signed-off-by: Rahul Pathak
Reviewed-by: Andrew Jones
---
disas/riscv.c | 2 --
target/riscv/cpu_bits.h | 2 --
2 files changed, 4 deletions(-)
diff --git a/d
XVentanaCondOps is Ventana custom extension. Add
its extension entry in the ISA Ext array
Signed-off-by: Rahul Pathak
---
This patch is based on branch riscv-to-apply.next (Alistair qemu tree)
Based on top commit: f2a91d8b78
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Hi Atish,
I tried your riscv_pmu_v12 branch but I couldn't made it working
without below change -
without this change qemu was not exporting the sscofpmf in the cpu dt nodes
-
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2e0dd6ddb5..2b36830755 100644
--- a/target/riscv/
gt; On Tue, Jun 28, 2022 at 3:03 AM Rahul Pathak wrote:
> >
> > mhartid csr is not available in user-mode code path and
> > user-mode build fails because of its reference in
> > riscv_cpu_realize function
> >
> > Commit causing the issue is currently in Alistair
ce disable extensions if priv spec
version does not match")
Signed-off-by: Rahul Pathak
---
Changes in V2:
- remove the stray format specifier
- add the Fixes tag and reference to external tree
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c
ce disable extensions if priv spec
version does not match")
Signed-off-by: Rahul Pathak
---
Changes in V2:
- remove the stray format specifier
- add the Fixes tag and reference to external tree
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c
Sorry for spamming but my send-email script misbehaved
and sent the v2 patch two times. Please ignore one of
the v2 patch
On Mon, Jun 27, 2022 at 10:20 PM Rahul Pathak wrote:
>
> mhartid csr is not available in user-mode code path and
> user-mode build fails because of its ref
Hi Bin, Victor,
Going to send the v2 by fixing these
silly mistakes.
Thanks
Rahul
On Mon, Jun 27, 2022 at 7:59 PM Bin Meng wrote:
>
> On Mon, Jun 27, 2022 at 5:40 PM Rahul Pathak wrote:
> >
> > mhartid csr is not available in user-mode code path and
> > user-mode bu
mhartid csr is not available in user-mode code path and
user-mode build fails because of its reference in
riscv_cpu_realize function
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
On Wed, Oct 27, 2021 at 8:14 AM Alistair Francis
wrote:
> On Mon, Oct 25, 2021 at 10:51 PM Rahul Pathak
> wrote:
> >
> > Patches add the mconfigptr csr support.
> > mconfigptr is newly incorporated in risc-v privileged architecture
> > specification 1.12 version
On Wed, Oct 27, 2021 at 8:08 AM Alistair Francis
wrote:
> On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak
> wrote:
> >
> > Signed-off-by: Rahul Pathak
> > ---
> > target/riscv/cpu.c | 4 +++-
> > target/riscv/cpu.h | 1 +
> > 2 files changed, 4 inserti
On Wed, Oct 27, 2021 at 8:13 AM Alistair Francis
wrote:
> On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak
> wrote:
> >
> > Signed-off-by: Rahul Pathak
> > ---
> > target/riscv/cpu_bits.h | 1 +
> > target/riscv/csr.c | 19 +++
>
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 4 +++-
target/riscv/cpu.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 788fa0b11c..83c3814a5a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -405,7 +405,9
Signed-off-by: Rahul Pathak
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 19 +++
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index cffcd3a5df..e2f154b7c5 100644
--- a/target/riscv/cpu_bits.h
ded privileged architecture spec version 1.12 ("v1.12.0") check
2. Added predicate function for mconfigptr which verifies
for priv spec version v1.12.0 or higher.
Thanks
Rahul
Rahul Pathak (2):
target/riscv: Add priv spec 1.12.0 version check
target/riscv: csr: Implement mconfigptr CSR
Hi Bin
On Thu, Oct 7, 2021 at 11:07 AM Bin Meng wrote:
>
> On Sun, Oct 3, 2021 at 7:29 PM Rahul Pathak wrote:
> >
> > mconfigptr is an mandatory CSR as per the priv spec.
>
> %s/an/a
>
Done
>
> as per the priv spec v1.12
>
> > This csr holds the phys
mconfigptr is an mandatory CSR as per the priv spec.
This csr holds the physical address of the configuration
data structure if this data structure is implemented
Its an readonly csr set to zero making configuration
data structure not supported.
Signed-off-by: Rahul Pathak
---
target/riscv
Hi Alistair,
One clarification: The unification of architectures is also going to allow
multi-arch CPUs (RV32/RV64) in a single machine instance? Or it's just
limited to only one in the runtime.
Rahul
On Tue, Sep 7, 2021 at 1:37 PM Ruinland ChuanTzu Tsai <
ruinl...@andestech.com> wrote:
> Hi Al
.sock.
I am unable to figure out what's wrong with unix\#serial1.sock
On Tue, Jun 1, 2021 at 7:48 PM Rahul Pathak
wrote:
> Hi Bin,
>
> Thanks for the response.
>
> I think the issue currently is that if I keep the "wait=on" and launch
> minicom on "unix\#seri
Rahul
On Tue, Jun 1, 2021 at 7:39 PM Bin Meng wrote:
> Hi Rahul,
>
> On Tue, Jun 1, 2021 at 11:12 AM Rahul Pathak
> wrote:
> >
> > Hi BIn,Alistair,
> >
> > I was passing the hss.elf file and it was strange that gdb after
> connecting was not letting the target
hul
On Tue, Jun 1, 2021 at 8:06 AM Bin Meng wrote:
> Hi Rahul,
>
> On Mon, May 31, 2021 at 10:43 PM Rahul Pathak
> wrote:
> >
> > On top of that, it seems I cannot connect with the target using gdb
> >
> > (gdb) target remote :1234
> > Remote
On top of that, it seems I cannot connect with the target using gdb
(gdb) target remote :1234
Remote debugging using :1234
bfd requires flen 8, but target has flen 0
Though the ABI is lp64 and ISA is rv64imac when the hss was built.
On Mon, May 31, 2021 at 7:37 PM Rahul Pathak
wrote:
>
en if I remove the serial1 like in the second case.
Thanks
Rahul
On Mon, May 31, 2021 at 8:19 AM Bin Meng wrote:
> Hi Rahul,
>
> On Mon, May 31, 2021 at 1:08 AM Rahul Pathak
> wrote:
> >
> > Hi Bin,
> >
> > I was reading a github issue which you raised for the is
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