Hello,
I keep seeing these warnings on the latest master with GCC 9.3:
/home/pranith/qemu/hw/block/pflash_cfi01.c: In function
‘pflash_mem_read_with_attrs’:
/home/pranith/qemu/hw/block/pflash_cfi01.c:667:20: note: parameter passing
for argument of type ‘MemTxAttrs’ {aka ‘struct MemTxAttrs’} chan
On Fri, Jun 21, 2019 at 1:21 AM Alex Bennée wrote:
> > * Register and memory read/write API
> >
> > It would be great to have register and memory read/write API i.e., ability
> > to read/write to registers/memory from within the callback. This gives the
> > plugin ability to do system intro
Hi Alex/Emilio,
I am really happy to see the progress you made on the plugin feature. Looking
forward to seeing it merged soon! Please CC me on future versions of the
patchset. I am happy to help review and contribute to this effort.
I have a few general comments from experience writing a very si
On Fri, Jun 14, 2019 at 10:24 AM Alex Bennée wrote:
>
> From: "Emilio G. Cota"
>
> Add the API first to ease review.
>
> Signed-off-by: Emilio G. Cota
> Signed-off-by: Alex Bennée
>
> ---
> v3
> - merge in changes to plugin install/reset/uninstall
> - split api file
> ---
> include/qemu/qe
Minor nits.
On Fri, Jun 14, 2019 at 11:41 AM Alex Bennée wrote:
>
> From: "Emilio G. Cota"
>
> Signed-off-by: Emilio G. Cota
> ---
> bsd-user/syscall.c | 9 +
> linux-user/syscall.c | 3 +++
> 2 files changed, 12 insertions(+)
>
> diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c
Hi,
On Fri, Jun 14, 2019 at 10:21 AM Alex Bennée wrote:
>
> This is mostly extracted from Emilio's more verbose commit comments
> with some additional verbiage from me.
>
> Signed-off-by: Alex Bennée
> ---
> docs/devel/index.rst | 1 +
> docs/devel/plugins.rst | 99 ++
On Mon, Sep 3, 2018 at 1:07 AM Michael Clark wrote:
>
> Thanks. I was just about to log an issue in the riscv-qemu issue tracker on
> GitHub.
>
> I reproduced it on my side. The fact that it is causes QEMU user to crash in
> translate.c is interesting.
>
> I ran your program with -d in_asm and i
On second looks, running the benchmark on a RISCV processor is also
giving a seg fault. So may be there is something wrong with the
benchmark... OTOH, x86 version runs fine... hmm
Please ignore this report, I will try to investigate further.
Thanks,
On Mon, Sep 3, 2018 at 12:45 AM Pranith Kumar
Hi Michael,
qemu-riscv64 seg faults for me on a static binary. You can build the
binary from here: https://github.com/pranith/quickht
$ STATIC=1 RISCV=1 make
$ qemu-riscv64 ./bench -t 1 -u 1
Thanks,
--
Pranith
Hi Alex,
On Tue, Sep 5, 2017 at 8:02 AM, Alex Bennée wrote:
>
> Pranith Kumar writes:
>
>> Update the comment which is not true since MTTCG.
>
> What happened to the cover letter? We seem to have a mix of patches but
> no summary of the overall outcome.
>
These are a
On Tue, Sep 5, 2017 at 5:50 PM, Richard Henderson wrote:
> On 08/29/2017 10:23 AM, Pranith Kumar wrote:
>> This patch increases the number of entries cached in the TLB. I went
>> over a few architectures to see if increasing it is problematic. Only
>> armv6 seems to have a l
CC'ing stable for 2.10.
On Tue, Aug 29, 2017 at 1:32 PM, Pranith Kumar wrote:
> Fix the following warning:
>
> /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is
> only applied to the left hand side of this bitwise operator
> [-Wlogical-not-parenthes
On Tue, Aug 29, 2017 at 5:16 PM, Emilio G. Cota wrote:
> On Sun, Aug 27, 2017 at 18:15:50 -0400, Pranith Kumar wrote:
>> Hi Emilio,
>>
>> On Fri, Jul 21, 2017 at 1:59 AM, Emilio G. Cota wrote:
>> > This will enable us to decouple code translation from the value
>
I should have worded the subject better. The warning is pointing to an
actual bug.
On Tue, Aug 29, 2017 at 1:32 PM, Pranith Kumar wrote:
> Fix the following warning:
>
> /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is
> only applied to the left hand
hand side expression to silence this warning
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^
Signed-off-by: Pranith Kumar
---
hw/intc/arm_gicv3_kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm
%) | 919.02(+3.6%) |
|10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |
|12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
The best combination for this workload came out to be 12 bits for the
TLB and a 16 entry vTLB cache.
Signed-off-by: Pranith Kumar
On Tue, Aug 29, 2017 at 11:01 AM, Richard Henderson
wrote:
> On 08/28/2017 11:33 PM, Pranith Kumar wrote:
>> + * TODO: rewrite this comment
>> */
>> -#define CPU_TLB_BITS
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.h | 2 ++
tcg/arm/tcg-target.h | 2 ++
tcg/ia64/tcg-target.h| 2 ++
tcg/mips/tcg-target.h| 2 ++
tcg/ppc/tcg-target.h | 2 ++
tcg/s390/tcg-target.h| 2 ++
tcg/sparc/tcg-target.h | 2 ++
7 files changed, 14 insertions
%) | 919.02(+3.6%) |
|10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |
|12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
The best combination for this workload came out to be 12 bits for the
TLB and a 16 entry vTLB cache.
Signed-off-by: Pranith Kumar
optimization pass.
This patch allows us to boot an x86 guest on ARM64 hosts using mttcg.
Signed-off-by: Pranith Kumar
---
tcg/tcg-op.c | 16
1 file changed, 16 insertions(+)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 87f673ef49..688d91755b 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg
Update the comment which is not true since MTTCG.
Reviewed-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
target/arm/translate-a64.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..f42b155d7d 100644
--- a
error margins, however I think
the
patch is still worth. We can also explore atomics instead of taking a lock for
the work item pool.
Signed-off-by: Pranith Kumar
---
cpus-common.c | 75 +++
1 file changed, 60 insertions(+), 15 deletions
On Mon, Aug 28, 2017 at 3:05 PM, Emilio G. Cota wrote:
> On Sun, Aug 27, 2017 at 23:53:25 -0400, Pranith Kumar wrote:
>> Using heaptrack, I found that quite a few of our temporary allocations
>> are coming from allocating work items. Instead of doing this
>> continou
On Mon, Aug 28, 2017 at 1:47 PM, Richard Henderson
wrote:
> On 08/27/2017 08:53 PM, Pranith Kumar wrote:
>> Using heaptrack, I found that quite a few of our temporary allocations
>> are coming from allocating work items. Instead of doing this
>> continously, we can cache th
On Mon, Aug 28, 2017 at 1:57 PM, Richard Henderson wrote:
> On 08/27/2017 08:53 PM, Pranith Kumar wrote:
>> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
>> index 55a46ac825..b41a248bee 100644
>> --- a/tcg/aarch64/tcg-target.h
>> +++ b/tcg/aarch6
Update the comment which is not true since MTTCG.
Signed-off-by: Pranith Kumar
---
target/arm/translate-a64.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..f42b155d7d 100644
--- a/target/arm/translate-a64.c
+++ b
oot+shutdown test).
Signed-off-by: Pranith Kumar
---
cpus-common.c | 85 ---
1 file changed, 70 insertions(+), 15 deletions(-)
diff --git a/cpus-common.c b/cpus-common.c
index 59f751ecf9..a1c4c7d1a3 100644
--- a/cpus-common.c
+++ b/c
optimization pass.
This patch allows us to boot an x86 guest on ARM64 hosts using mttcg.
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.h | 2 ++
tcg/arm/tcg-target.h | 2 ++
tcg/mips/tcg-target.h| 2 ++
tcg/ppc/tcg-target.h | 2 ++
tcg/tcg-op.c | 17
Hi Emilio,
On Fri, Jul 21, 2017 at 1:59 AM, Emilio G. Cota wrote:
> This will enable us to decouple code translation from the value
> of parallel_cpus at any given time. It will also help us minimize
> TB flushes when generating code via EXCP_ATOMIC.
>
> Note that the declaration of parallel_cpus
On Thu, Aug 24, 2017 at 11:58 AM, Pranith Kumar wrote:
> This patch increases the number of entries cached in the TLB. I went
> over a few architectures to see if increasing it is problematic. Only
> armv6 seems to have a limitation that only 8 bits can be used for
> indexing these
(+3.6%) |
|10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |
|12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
The best combination for this workload came out to be 12 bits for the
TLB and a 16 entry vTLB cache.
Signed-off-by: Pranith Kumar
On Mon, Aug 7, 2017 at 7:07 AM, Eric Blake wrote:
> On 08/05/2017 01:52 PM, Pranith Kumar wrote:
>> FYI,
>>
>> This commit breaks the build with gcc-7:
>>
>> CC block/vvfat.o
>> qemu/block/vvfat.c: In function ‘read_directory’:
>> qemu/block/vv
FYI,
This commit breaks the build with gcc-7:
CC block/vvfat.o
qemu/block/vvfat.c: In function ‘read_directory’:
qemu/block/vvfat.c:605:37: error: ‘__builtin___sprintf_chk’ may write
a terminating nul past the end of the destination
[-Werror=format-overflow=]
int len = sprintf
4K-sized cache.
Signed-off-by: Pranith Kumar
---
include/exec/cpu-defs.h | 5 -
tcg/aarch64/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 2 ++
tcg/mips/tcg-target.h| 1 +
tcg/s390/tcg-target.h| 1 +
tcg/sparc/tcg-target.h | 1 +
6 files changed, 10 insertions(+), 1 deletion
On Wed, Jul 12, 2017 at 7:08 PM, Richard Henderson wrote:
> On 07/12/2017 12:14 PM, Pranith Kumar wrote:
>>
>> Use ADR instruction for shorter jumps.
>>
>> I was going through rth's email and realized that I should have done
>> this the first ti
Use ADR instruction for shorter jumps.
I was going through rth's email and realized that I should have done
this the first time.
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/tcg/aarch6
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Pranith Kumar
---
hw/i386/kvmvapic.c | 101 +
1 file changed, 55 insertions(+), 46 deletions(-)
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 0d9ef77580
Now that we have proper locking after MTTCG patches have landed, we
can revert the commit. This reverts commit
a9353fe897ca2687e5b3385ed39e3db3927a90e0.
CC: Peter Maydell
CC: Alex Bennée
Signed-off-by: Pranith Kumar
---
exec.c | 25 +++--
1 file changed, 19 insertions
nt modifier 'w' is not (yet?) accepted by gcc. Fix this by increasing
the ctr size.
Signed-off-by: Pranith Kumar
---
util/cacheinfo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/cacheinfo.c b/util/cacheinfo.c
index f987522df4..6253049533 100644
--- a/util/c
We use ADRP+ADD to compute the target address for goto_tb. This patch
introduces the NOP instruction which is used to align the above
instruction pair so that we can use one atomic instruction to patch
the destination offsets.
CC: Richard Henderson
CC: Alex Bennée
Signed-off-by: Pranith Kumar
We can use a branch to register instruction for exit_tb for offsets
greater than 128MB.
CC: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64
This patch enables the indirect jump path using an LDR (literal)
instruction. It will be interesting to test and see which performs
better among the two paths.
CC: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 42
On Fri, Jun 30, 2017 at 12:47 AM, Richard Henderson wrote:
> On 06/29/2017 05:40 PM, Pranith Kumar wrote:
>>
>> void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
>> {
>> tcg_insn_unit *code_ptr = (tcg_insn_unit *)jmp_addr;
>> -tcg_i
We use ADRP+ADD to compute the target address for goto_tb. This patch
introduces the NOP instruction which is used to align the above
instruction pair so that we can use one atomic instruction to patch
the destination offsets.
CC: Richard Henderson
CC: Alex Bennée
Signed-off-by: Pranith Kumar
remove
the code buffer size limitation altogether. However, I feel that 3GB
should be sufficient for now and hence did not change it ;). It
however enables the !USE_DIRECT_JUMP path on aarch64 hosts.
Thanks,
v3:
* Update with comments and reviews by Richard
Pranith Kumar (3):
tcg/aarch64
This patch enables the indirect jump path using an LDR (literal)
instruction. It will be interesting to test and see which performs
better among the two paths.
CC: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 42
We can use a branch to register instruction for exit_tb for offsets
greater than 128MB.
CC: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64
We can use a branch to register instruction for exit_tb for offsets
greater than 128MB.
CC: Richard Henderson
CC: Alex Bennée
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg
This patch enables the indirect jump path using an LDR (literal)
instruction. It will be interesting to test and see which performs
better among the two paths.
CC: Richard Henderson
CC: Alex Bennée
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 42
We use ADRP+ADD to compute the target address for goto_tb. This patch
introduces the NOP instruction which is used to align the above
instruction pair so that we can use one atomic instruction to patch
the destination offsets.
CC: Richard Henderson
CC: Alex Bennée
Signed-off-by: Pranith Kumar
remove
the code buffer size limitation altogether. However, I feel that 3GB
should be sufficient for now and hence did not change it ;). It
however enables the !USE_DIRECT_JUMP path on aarch64 hosts.
Thanks,
Pranith Kumar (3):
tcg/aarch64: Introduce and use long branch to register
tcg/aarch64
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Pranith Kumar
---
hw/i386/kvmvapic.c | 73 +++---
1 file changed, 42 insertions(+), 31 deletions(-)
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 82a49556af
Now that we have proper locking after MTTCG patches have landed, we
can revert the commit. This reverts commit
a9353fe897ca2687e5b3385ed39e3db3927a90e0.
CC: Peter Maydell
CC: Alex Bennée
Signed-off-by: Pranith Kumar
---
exec.c | 25 +++--
1 file changed, 19 insertions
Hello,
Please find these two pending MTTCG fixes I have in my repo.
I've reworked the async_safe_* patch according to pbonzini's suggestion.
Thanks,
Pranith Kumar (2):
Revert "exec.c: Fix breakpoint invalidation race"
mttcg/i386: Patch instruction using async_safe_
I used the following patch to collect hit/miss TLB ratios for a few
benchmarks. The results can be found here: http://imgur.com/a/gee1o
Please note that these results also include boot/shutdown as the
per-region instrumentation patch came later.
Signed-off-by: Pranith Kumar
---
accel/tcg
));
#define magic_disable() \
asm volatile ("msr pmuserenr_el0, %0" :: "r" (0xfa11dead));
Signed-off-by: Pranith Kumar
---
target/arm/helper.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 25
The following two patches are what I use to instrument guest code and
collect TLB hit/miss information. These patches are for informational
and discussion purposes only.
Pranith Kumar (2):
[TEST] aarch64: Use pmuserenr_el0 register for instrumentation
[TEST] Collect TLB stats along with
> - calculate the tb_jmp_cache hash once
>
> Signed-off-by: Alex Bennée
> ---
> tcg-runtime.c | 35 +++
> 1 file changed, 19 insertions(+), 16 deletions(-)
Phew, glad you got this figured out! I tested it on the images I have
and it works. Plea
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 1fa3bccc89..ab0a8caa03 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg
Hi,
The following patches apply on top of tcg-next of rth's branch. These
patches make use of LDR (literal) on aarch64 and enable us to remove
the 128MB code buffer size limitation.
Pranith Kumar (3):
tcg/aarch64: Introduce and use jump to register
tcg/aarch64: Introdue LDR (li
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index ab0a8caa03..e488aacadb 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -269,6
This enables indirect jump on aarch64 hosts. Tested by booting an x86 guest on
aarch64 host.
Signed-off-by: Pranith Kumar
---
include/exec/exec-all.h | 6 +-
tcg/aarch64/tcg-target.inc.c | 25 ++---
translate-all.c | 2 --
3 files changed, 7
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Pranith Kumar
---
hw/i386/kvmvapic.c | 82 ++
1 file changed, 52 insertions(+), 30 deletions(-)
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 82a49556af
On Wed, Jun 7, 2017 at 2:09 PM, Alex Bennée wrote:
>
> Pranith Kumar writes:
>
>> Can someone please pick this up?
>
> It needs to be re-posted with the review tag and ping Paolo re: async
> work for KVM.
>
Will do.
Thanks,
--
Pranith
Now that we have proper locking after MTTCG patches have landed, we
can revert the commit. This reverts commit
a9353fe897ca2687e5b3385ed39e3db3927a90e0.
CC: Peter Maydell
CC: Alex Bennée
Signed-off-by: Pranith Kumar
---
exec.c | 25 +++--
1 file changed, 19 insertions
Can someone please pick this up?
Thanks,
On Fri, Feb 24, 2017 at 12:42 AM, Pranith Kumar wrote:
> In mttcg, calling pause_all_vcpus() during execution from the
> generated TBs causes a deadlock if some vCPU is waiting for exclusive
> execution in start_exclusive(). Fix this by
nderson
> Suggested-by: Geert Martin Ijewski
> Tested-by:Geert Martin Ijewski
> Signed-off-by: Emilio G. Cota
> ---
Reviewed-by: Pranith Kumar
--
Pranith
On Mon, Jun 5, 2017 at 6:49 PM, Emilio G. Cota wrote:
> Signed-off-by: Emilio G. Cota
Reviewed-by: Pranith Kumar
> ---
> tests/atomic_add-bench.c | 4 ++--
> tests/qht-bench.c| 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/tests/atomi
On Mon, Jun 5, 2017 at 6:49 PM, Emilio G. Cota wrote:
> This is a constant used as a hint for padding structs to hopefully avoid
> false cache line sharing.
>
> The constant can be set at configure time by defining QEMU_CACHELINE_SIZE
> via --extra-cflags. If not set there, we try to obtain the va
5172.html
> Subject: Re: GSoC 2017 Proposal: TCG performance enhancements
> Message-ID: <1e67644b-4b30-887e-d329-1848e94c9...@twiddle.net>
Reviewed-by: Pranith Kumar
Thanks for doing this Emilio. Do you plan to continue working on rth's
suggestions in that email? If so, can we co-ordinate our work?
--
Pranith
Hi Alex,
Please find some comments and questions below:
On Wed, May 17, 2017 at 10:52 AM, Alex Bennée wrote:
> This is a simple helper script to extract TLB flush stats from the a
> simpletrace file and plot the results.
>
> Signed-off-by: Alex Bennée
>
> ---
> v2
> - re-factored for new trac
On Sun, May 14, 2017 at 5:12 PM, Richard Henderson wrote:
>>
> Surely you'd also want to make this change for 0x11a and 0x11b. Which would
> also simplify that code a bit.
>
> That said, there's *lots* of missing LOCK prefix checks. What brings this
> one in particular to your attention?
>
The
The instruction "lock nopl (%rax)" should raise an exception. However,
we don't do that since we do not check for lock prefix for nop
instructions. The following patch adds this check and makes the
behavior similar to hardware.
Signed-off-by: Pranith Kumar
---
target/i386/transla
On Thu, Dec 29, 2016 at 5:04 AM, Andrew Jones wrote:
> On Thu, Dec 29, 2016 at 08:02:16AM -, Hansni Bu wrote:
>> Public bug reported:
> ...
>> https://bugs.launchpad.net/bugs/1653063
> ...
>> After console prints the message below:
>> "Uncompressing
>> Linux...
On Wed, Apr 19, 2017 at 10:26 PM, Eduardo Habkost wrote:
> On Wed, Apr 19, 2017 at 06:03:01PM -0400, Pranith Kumar wrote:
>> On Wed, Apr 19, 2017 at 5:33 PM, Eduardo Habkost wrote:
>> > On Wed, Apr 19, 2017 at 05:25:23PM -0400, Pranith Kumar wrote:
>> >> On Wed, Ap
On Wed, Apr 19, 2017 at 5:33 PM, Eduardo Habkost wrote:
> On Wed, Apr 19, 2017 at 05:25:23PM -0400, Pranith Kumar wrote:
>> On Wed, Apr 19, 2017 at 4:57 PM, Eduardo Habkost wrote:
>> > On Wed, Apr 19, 2017 at 04:16:53PM -0400, Pranith Kumar wrote:
>> >> On Wed, Ap
On Wed, Apr 19, 2017 at 4:57 PM, Eduardo Habkost wrote:
> On Wed, Apr 19, 2017 at 04:16:53PM -0400, Pranith Kumar wrote:
>> On Wed, Apr 19, 2017 at 4:13 PM, Eduardo Habkost wrote:
>> > On Wed, Apr 19, 2017 at 04:00:49PM -0400, Pranith Kumar wrote:
>> >> On Wed, Ap
On Wed, Apr 19, 2017 at 4:13 PM, Eduardo Habkost wrote:
> On Wed, Apr 19, 2017 at 04:00:49PM -0400, Pranith Kumar wrote:
>> On Wed, Apr 19, 2017 at 3:54 PM, Pranith Kumar wrote:
>> > When we enable hyperthreading (using threads smp argument), we warn
>> > the user if
On Wed, Apr 19, 2017 at 3:54 PM, Pranith Kumar wrote:
> When we enable hyperthreading (using threads smp argument), we warn
> the user if the cpu is an AMD cpu. This does not make sense on TCG and
> is also obsolete now that AMD Ryzen support hyperthreading.
>
> Fix this by adding
.
Signed-off-by: Pranith Kumar
---
target/i386/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 13c0985f11..f34bb5ead7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -202,12 +202,12 @@ static void
.
Signed-off-by: Pranith Kumar
---
target/i386/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 13c0985f11..f34bb5ead7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -202,12 +202,12 @@ static void
On Tue, Apr 18, 2017 at 5:56 AM, Paolo Bonzini wrote:
>
>
> On 17/04/2017 20:55, Pranith Kumar wrote:
>>>> +/* ARM does not have a user-space readble cycle counter available.
>>>> + * This is a compromise to get monotonically increasing time.
>
Tested and confirmed that the stretch i386 debian qcow2 image on a
raspberry pi 2 works.
Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/>
Signed-off-by: Pranith Kumar
---
include/qemu/timer.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/includ
On Mon, Apr 17, 2017 at 2:42 PM, Peter Maydell wrote:
> On 15 April 2017 at 20:29, Pranith Kumar wrote:
>> Tested and confirmed that the stretch i386 debian qcow2 image on a
>> raspberry pi 2 works.
>>
>> Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/8932
Tested and confirmed that the stretch i386 debian qcow2 image on a
raspberry pi 2 works.
Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/>
Signed-off-by: Pranith Kumar
---
include/qemu/timer.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/qemu/tim
On Thu, Mar 23, 2017 at 4:05 AM, Igor R wrote:
> Hi,
>
> I'm trying to use the deterministic record/replay feature, and I would
> like to know which commit I should take to get it work.
> In RC0 it seems to be broken. I tried pre-MTTCG commit 2421f381dc, as
Can you retry with the latest rc? There
TCG uses the AMD cpu which warns when we use hyperthreading. Disable
the warning for TCG since it is not necessary.
Signed-off-by: Pranith Kumar
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7aa762245a
On Mon, Mar 27, 2017 at 11:03 PM, Pranith Kumar wrote:
>
> If you think the project makes sense, I will add it to the GSoC wiki
> so that others can also apply for it. Please let me know if you are
> interested in mentoring it along with Alex.
>
One other thing is if you think t
Hi Paolo,
On Mon, Mar 27, 2017 at 7:32 AM, Paolo Bonzini wrote:
>
>
> On 25/03/2017 17:52, Pranith Kumar wrote:
>> * Implement an LRU translation block code cache.
>>
>> In the current TCG design, when the translation cache fills up, we flush
>> all
>>
Hi Richard,
Thanks for the feedback. Please find some comments inline.
On Mon, Mar 27, 2017 at 6:57 AM, Richard Henderson wrote:
>
> 128MB is really quite large. I doubt doubling the cache size will really
> help that much. That said, it's really quite trivial to make this change,
> if you'd l
Hi Stefan,
On Mon, Mar 27, 2017 at 11:54 AM, Stefan Hajnoczi wrote:
> On Sat, Mar 25, 2017 at 12:52:35PM -0400, Pranith Kumar wrote:
>> Alex Bennée, who mentored me last year, has agreed to mentor me again this
>> time if the proposal is accepted.
>
> Thanks, the project ide
Hello,
With MTTCG code now merged in mainline, I tried to see if we are able to run
x86 SMP guests on ARM64 hosts. For this I tried running a windows XP guest on
a dragonboard 410c which has 1GB RAM. Since x86 has a strong memory model
whereas ARM64 is a weak memory model, I added a patch to gener
ni
Reported-by: Jann Horn
Signed-off-by: Pranith Kumar
---
target/i386/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 72c1b03a2a..1d1372fb43 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -
This fixes the bug: 'user-to-root privesc inside VM via bad translation
caching' reported by Jann Horn here:
https://bugs.chromium.org/p/project-zero/issues/detail?id=1122
CC: Richard Henderson
CC: Peter Maydell
CC: Paolo Bonzini
Reported-by: Jann Horn
Signed-off-by: Pra
On Thu, Mar 23, 2017 at 1:37 PM, Paolo Bonzini wrote:
>
>
> On 23/03/2017 17:50, Pranith Kumar wrote:
>> On Thu, Mar 23, 2017 at 6:27 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 22/03/2017 21:01, Richard Henderson wrote:
>>>>>
>>>>
Hi Jed,
On Mon, Mar 20, 2017 at 2:35 AM, Wangjintang wrote:
> Hi,
>
> We see that armv8's prefetch instruction decode have been skipped in
> qemu. For some user, they need prefetch instruction, for example, they use
> qemu to generate the instruction trace. We want to merge this patch t
On Thu, Mar 23, 2017 at 6:27 AM, Paolo Bonzini wrote:
>
>
> On 22/03/2017 21:01, Richard Henderson wrote:
>>>
>>> Ah, OK. Thanks for the explanation. May be we should check the size of
>>> the instruction while decoding the prefixes and error out once we
>>> exceed the limit. We would not generate
On Wed, Mar 22, 2017 at 11:21 AM, Peter Maydell
wrote:
> On 22 March 2017 at 15:14, Pranith Kumar wrote:
>> On Wed, Mar 22, 2017 at 11:04 AM, Peter Maydell
>> wrote:
>>> This doesn't look right because it means we'll check
>>> only after we'v
On Wed, Mar 22, 2017 at 11:04 AM, Peter Maydell
wrote:
>>
>> How about doing the instruction size check as follows?
>>
>> diff --git a/target/i386/translate.c b/target/i386/translate.c
>> index 72c1b03a2a..94cf3da719 100644
>> --- a/target/i386/translate.c
>> +++ b/target/i386/translate.c
>> @@ -8
On Mon, Mar 20, 2017 at 10:46 AM, Peter Maydell wrote:
> On 20 March 2017 at 14:36, Jann Horn wrote:
>> This is an issue in QEMU's system emulation for X86 in TCG mode.
>> The issue permits an attacker who can execute code in guest ring 3
>> with normal user privileges to inject code into other pr
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